CDR
Understanding CDR
Timing Extraction and Serial Link Integrity
In high-speed parallel interfaces, a separate clock signal is routed alongside the data lines. However, at data rates above 10 Gbps (such as PCIe Gen 4/5/6, USB4, HDMI 2.1, and 100G/400G Ethernet), this approach fails due to channel skew, pin count constraints, and crosstalk. High-speed serial interfaces address this by embedding the clock signal within the data stream. The data is encoded (using schemes like 64b/66b or PAM4) to ensure frequent transitions.
At the receiver, the Clock and Data Recovery (CDR) circuit is responsible for extracting this embedded timing. The CDR generates a clean recovered clock that is synchronized in phase and frequency with the incoming data transitions. This recovered clock is then used to sample the data at the center of the data eye (the unit interval, UI), where the signal amplitude is maximized and the bit error rate (BER) is lowest.
Phase-Locked Loop (PLL) Architectures and Jitter Tolerance
Most high-speed CDR circuits are based on a Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) architecture. The phase detector compares the relative timing of the incoming data transitions against the edges of the recovered clock. A common architecture is the Alexander (bang-bang) phase detector, which samples the signal three times per bit period: at the center of the previous bit, at the transition boundary, and at the center of the current bit. This ternary output indicates whether the clock is early or late.
A key performance metric of a CDR is its jitter tolerance, which defines the amplitude and frequency of timing noise (jitter) the CDR can tolerate on the incoming signal without causing bit errors. Below the CDR's loop bandwidth, the loop tracks the jitter (the recovered clock moves with the jitter), keeping the sampling point centered. Above the loop bandwidth, the CDR cannot track the jitter, and the tolerance drops to approximately half the unit interval ($0.5$ UI).
Key Mathematical Relations
Technical Specifications Comparison
| Interface Standard | Line Rate | CDR Loop Bandwidth | Minimum Jitter Tolerance (High Freq) | Line Encoding | Primary Channel Type |
|---|---|---|---|---|---|
| 10G Ethernet (10GBASE-R) | 10.3125 Gbps | 4 MHz | 0.30 UI | 64b/66b (NRZ) | Optical fiber / backplane |
| PCIe Gen 5 | 32.0 GT/s | 10 MHz | 0.25 UI | 128b/130b (NRZ) | FR4/Megtron6 PCB trace |
| 56G PAM4 (OIF) | 28.0 Gbaud (56 Gbps) | 15 MHz | 0.22 UI | PAM4 + RS-FEC | High-speed backplane |
| 112G PAM4 | 53.125 Gbaud (106 Gbps) | 20 - 40 MHz | 0.20 UI | PAM4 + RS-FEC | Chip-to-module / optical |
Frequently Asked Questions
What is the difference between PLL-based and oversampling CDR architectures?
PLL-based CDRs use a phase-locked loop to continuously adjust the phase of a local oscillator to match the data transitions. Oversampling CDRs sample the incoming data at multiple times the bit rate (typically 3x to 5x) and use digital logic to select the sample closest to the center of the data eye, avoiding the need for an analog VCO.
How does line encoding help the CDR circuit?
A CDR requires transitions (edges) to estimate phase error. If the transmitter sends a long string of consecutive zeros or ones, the CDR receives no timing information and the VCO frequency will drift, causing synchronization loss. Line encoding (like 64b/66b or scrambling) guarantees a minimum density of transitions, keeping the CDR locked.
What is CDR jitter transfer?
Jitter transfer is a measurement that characterizes how much of the jitter on the incoming data stream is transferred to the recovered clock. It behaves as a low-pass filter: low-frequency jitter is transferred to the clock, while high-frequency jitter is filtered out.