How does loop bandwidth affect phase noise?

Inside the loop bandwidth, the PLL output phase noise follows the reference oscillator's phase noise multiplied by 20 log10(N), where N is the divider ratio. Outside the loop bandwidth, the output phase noise follows the VCO's free-running phase noise. The optimal loop bandwidth is at the crossover point where the multiplied reference noise equals the VCO noise. Making the loop wider than this crossover adds noise from the reference; making it narrower allows the VCO's high close-in noise to dominate. For a typical integer-N PLL at 3.5 GHz with 10 MHz reference (N = 350): the 20 log10(350) = 51 dB of noise multiplication means the reference OCXO's minus 155 dBc/Hz at 10 kHz becomes minus 104 dBc/Hz at the output.

What is the difference between integer-N and fractional-N PLLs?

An integer-N PLL can only produce output frequencies that are integer multiples of the reference frequency. To achieve fine frequency steps (e.g., 200 kHz for GSM channels), the reference must be lowered to 200 kHz, forcing a high divider ratio N that multiplies the reference noise by 20 log10(N) and requires a very narrow loop bandwidth (less than f_ref/10), resulting in slow lock time. A fractional-N PLL allows non-integer divider ratios by alternating between N and N+1 on each reference cycle, producing an average division ratio with fractional resolution. This allows a much higher reference frequency (10 to 100 MHz), reducing N and enabling wider loop bandwidth for better phase noise and faster lock time. The penalty is fractional spurs at offsets related to the fractional part.

How fast can a PLL lock to a new frequency?

Lock time is approximately 5 to 10 divided by the loop bandwidth for settling to within 1 degree of final phase. A PLL with 100 kHz loop bandwidth locks in about 50 to 100 microseconds. A narrow-band PLL with 1 kHz bandwidth takes 5 to 10 milliseconds. Frequency hopping systems (military radios, Bluetooth) need microsecond lock times, requiring loop bandwidths of 500 kHz to 1 MHz. Radar synthesizers for pulse-Doppler systems may need lock times under 10 microseconds, pushing loop bandwidths above 1 MHz and requiring fractional-N architectures with sigma-delta modulators to achieve both wide bandwidth and low spur levels.

Active Components

PLL

Phase-Locked Loop

A crystal oscillator provides exquisite frequency stability but is fixed at one frequency. A VCO is freely tunable but drifts with temperature, supply voltage, and aging. A PLL combines the best of both: it locks the VCO's output phase to a stable reference by dividing the VCO frequency by N, comparing the phase to the reference, and feeding back a correction voltage through a loop filter. The result is a synthesizer that produces any frequency on a grid of f_ref/N with the reference's long-term stability and the VCO's tuning range. Every radio, radar, cellular base station, and test instrument contains at least one PLL.

Category: Active Components

Output: f_out = N × f_ref

Key Spec: Loop bandwidth (Hz)

The Feedback Loop That Makes Synthesizers Work

Architecture	Frequency Step	Reference	Phase Noise	Lock Time	Spurs
Integer-N	= f_ref	Must equal channel spacing	Higher (large N)	Slower (narrow BW)	Low
Fractional-N (MMD)	< f_ref	High (10 to 50 MHz)	Lower (small N)	Fast	Moderate
Fractional-N (ΣΔ)	Sub-Hz possible	High (50 to 200 MHz)	Lowest	Fastest	Low (randomized)
DDS + PLL	Sub-Hz	Fixed	Good	Very fast	DDS harmonics

Output frequency:
f_out = N × f_ref (integer-N)
f_out = (N + F/M) × f_ref (fractional-N)

In-band phase noise floor (reference-limited):
L_in-band = L_ref(f_m) + 20·log₁₀(N) + L_PD+CP

Lock time estimate:
t_lock ≈ 5 to 10 / f_{loop BW}

For a 3.5 GHz synthesizer with 100 kHz loop BW: lock time ≈ 50 to 100 μs.
For a frequency-hopping radio with 1 MHz loop BW: lock time ≈ 5 to 10 μs.

Common Questions

Frequently Asked Questions

How does loop BW affect phase noise?

Inside the loop BW: output PN follows the reference × 20·log(N). Outside: follows VCO free-running noise. Optimal BW is at the crossover where multiplied reference noise equals VCO noise. Wider than crossover adds reference noise; narrower lets VCO noise dominate.

Integer-N vs. fractional-N?

Integer-N: step = f_ref, needs low reference for fine steps, high N multiplies noise. Fractional-N: uses high reference (50+ MHz), low N, wider loop BW for better noise and faster lock. Penalty: fractional spurs, mitigated by ΣΔ modulators.

How fast does a PLL lock?

t_lock ≈ 5 to 10 / loop BW. 100 kHz BW: ~75 μs. 1 MHz BW: ~7 μs. Frequency hopping and radar need microsecond lock, requiring wide-BW fractional-N with ΣΔ modulators.

Related Terms

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Synthesizer Design

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