Why does charge pump current mismatch cause reference spurs?

When locked, the PFD ideally produces zero-width UP and DOWN pulses and the charge pump outputs no net current. In practice, a small anti-backlash pulse of fixed width (1 to 5 ns) activates both UP and DOWN switches simultaneously every reference cycle. If the UP current (sourcing from VDD) and DOWN current (sinking to ground) are not perfectly matched, a net charge packet leaks into the loop filter at the reference frequency, modulating the VCO control voltage and creating sidebands (spurs) at offsets of plus and minus f_ref from the carrier. A 1 percent current mismatch in a charge pump with 5 mA nominal current and 2 ns anti-backlash pulse at 10 MHz reference produces approximately minus 65 dBc reference spurs.

What is the dead zone problem?

If the charge pump switches have a finite turn-on time and the phase error is very small, the UP or DOWN pulse may be too short to fully turn on the current source. The charge pump then delivers less current than expected, reducing the loop gain for small phase errors and creating a dead zone where the PLL does not correct small frequency offsets. The result is increased jitter and phase noise near the carrier. The standard solution is the anti-backlash circuit: even at zero phase error, both UP and DOWN pulses have a minimum width (1 to 5 ns), ensuring both current sources are always fully active.

How does charge pump current affect PLL loop bandwidth?

The charge pump current Icp directly sets the loop gain, and therefore the loop bandwidth. For a type-2, third-order PLL with a passive loop filter: the loop bandwidth is proportional to Icp times Kvco divided by N (the feedback divider ratio). Doubling Icp doubles the loop bandwidth if all other components stay fixed. Modern fractional-N synthesizers like the ADF4356 have programmable charge pump currents from 0.3 to 5.4 mA in 16 steps, allowing the designer to tune the loop bandwidth after board assembly.

Active Components

Charge Pump

In a phase-locked loop, the phase-frequency detector (PFD) outputs digital pulses: UP when the reference leads, DOWN when it lags. The VCO needs an analog voltage. The charge pump bridges this gap by injecting or removing a precise current pulse into a capacitor. Each reference cycle deposits or withdraws a charge packet proportional to the phase error, and the loop filter integrates these packets into the smooth control voltage the VCO requires. The accuracy of this conversion, specifically how well the UP and DOWN currents match, determines whether the PLL has clean spectral purity or is polluted by reference spurs.

Category: Active Components

Typical I_cp: 0.5 to 5 mA

Key Spec: Current match (<1%)

Turning Phase Error Pulses into a Control Voltage

The charge pump contains two switched current sources: one sourcing current from V_DD (activated by the UP pulse) and one sinking current to ground (activated by the DOWN pulse). When the PFD detects a phase lead, the UP switch closes and current flows into the loop filter capacitor, raising the VCO control voltage and increasing the output frequency. When the PFD detects a lag, the DOWN switch opens and current drains from the capacitor.

Charge Pump Specifications Across PLL Families

PLL IC	I_cp Range	Current Match	Ref Spurs (typical)	Max f_ref
ADF4351	0.31 to 5.0 mA	±2%	−60 to −70 dBc	32 MHz
ADF4356	0.3 to 5.4 mA	±1.5%	−70 to −80 dBc	125 MHz
LMX2594	0.0625 to 15 mA	±0.5%	−80 to −95 dBc	200 MHz
HMC835	0.02 to 2.56 mA	±1%	−85 to −100 dBc	100 MHz

Reference Spur Estimation from Current Mismatch

Spur level from charge pump mismatch:
P_spur ≈ 20·log₁₀(ΔI × t_pulse × f_ref × K_VCO / (2π × f_offset))

Quick estimate for small mismatch:
P_spur ≈ 20·log₁₀(ΔI/I_cp) + 20·log₁₀(t_pulse × f_ref) − 20·log₁₀(loop attenuation)

A 1% mismatch (−40 dB) with 2 ns pulses at 10 MHz reference (−37 dB duty cycle) and 20 dB of loop filter attenuation at f_ref gives approximately −40 − 37 − 20 = −97 dBc. In practice, charge sharing and PFD reset delay add 10 to 20 dB, yielding −75 to −85 dBc.

Common Questions

Frequently Asked Questions

Why does current mismatch cause reference spurs?

At lock, anti-backlash pulses activate both UP and DOWN switches every reference cycle. If the currents differ, a net charge packet leaks into the loop filter at f_ref, modulating the VCO. 1% mismatch with 5 mA and 2 ns pulses at 10 MHz produces approximately −65 dBc spurs.

What is the dead zone?

If charge pump switches take too long to turn on, very small phase errors produce no corrective current, creating a dead zone with increased jitter. The anti-backlash circuit forces a minimum pulse width (1 to 5 ns) to keep both sources active even at zero phase error.

How does I_cp affect loop bandwidth?

Loop BW is proportional to I_cp × K_VCO / N. Doubling I_cp doubles the BW. Modern synthesizers (e.g., ADF4356) have programmable I_cp in 16 steps to tune the loop after board assembly.

Related Terms

← Channel Spacing CP Linearization →

PLL Design

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