Why replace the analog PLL?

Moore's Law. As silicon chips shrink to 5nm and below, digital transistors become incredibly fast and cheap. However, analog circuits (like the massive capacitors required for an analog loop filter) do not shrink. If you put an analog PLL on a 5nm chip, the analog filter capacitors will consume 80% of the expensive silicon area. By switching to an All-Digital PLL, the giant analog capacitors are replaced by a few lines of DSP code, allowing the PLL to shrink in tandem with the digital logic.

How does it measure phase digitally?

An analog PLL uses a mixer to multiply voltages to find the phase difference. An ADPLL uses a Time-to-Digital Converter (TDC). A TDC is essentially an ultra-fast digital stopwatch. It measures the exact time delay (in picoseconds) between the rising edge of the reference clock and the rising edge of the oscillator. This time delay is converted directly into a binary number (e.g., 011010) representing the phase error, which is then fed into the digital processor.

What is a Digitally Controlled Oscillator (DCO)?

In an analog PLL, the frequency is tuned by changing a continuous analog voltage applied to a varactor diode (VCO). In an ADPLL, there is no analog voltage. A DCO is tuned by an array of hundreds of microscopic capacitors that can be switched on or off via binary code. If the digital processor wants to lower the frequency, it simply sends a binary command to switch on more capacitors. It is a discrete, stepped tuning process rather than a continuous analog sweep.

System Design

All-Digital PLL (ADPLL)

A semiconductor company wants to build a complete Bluetooth transceiver on a single, ultra-cheap 7nm CMOS silicon chip. The massive digital processor fits easily on the chip, but the analog RF synthesizer (the PLL) is a problem. The analog loop filter requires large, physical capacitors that take up too much silicon real estate, making the chip too expensive. The engineers scrap the analog design and build an All-Digital PLL (ADPLL). They replace the analog phase detector with a digital stopwatch (a TDC) that measures the phase error as a binary number. They replace the giant analog filter capacitors with a tiny block of DSP code (a digital filter). Finally, they replace the analog oscillator with a Digitally Controlled Oscillator (DCO) that tunes the frequency by switching microscopic capacitors on and off. The entire synthesizer is now built out of standard digital logic gates, shrinking the chip size by 80% and allowing it to be manufactured entirely on cheap 7nm digital silicon.

Category: System Design

Architecture: TDC + Digital Loop Filter + DCO

Primary Advantage: Scales perfectly with Moore's Law (CMOS integration)

Analog PLL vs. All-Digital PLL

Component Function	Analog PLL Implementation	ADPLL Implementation
Phase Error Detection	Analog Multiplier / Charge Pump (Current)	Time-to-Digital Converter (Binary Data)
Loop Filter	Massive physical Resistors & Capacitors	Digital Signal Processor (DSP Code)
Oscillator Tuning	Continuous Analog Voltage (VCO)	Discrete Binary Switching (DCO)
CMOS Scaling Capability	Poor (Analog components don't shrink well)	Excellent (Pure logic gates shrink perfectly)

Quantization Noise:
Because the ADPLL is a digital system, it suffers from quantization error. The Time-to-Digital Converter (TDC) is not infinitely precise; it measures time in discrete "steps" (e.g., 5 picosecond increments). If the true phase error is 7 picoseconds, the TDC must round it to 5 or 10. This rounding error creates a constant, high-frequency digital jitter known as Quantization Noise, which ultimately limits the phase noise floor of the ADPLL compared to a pristine analog design.

DCO Frequency Resolution:
Δf = f_step
The oscillator cannot sweep continuously. It jumps from one frequency to the next based on the size of the smallest switchable capacitor in its bank. To achieve high resolution, designers must use "Sigma-Delta Dithering" to rapidly toggle a capacitor on and off, artificially creating an average frequency step that is smaller than the physical capacitor allows.

Common Questions

Frequently Asked Questions

Can you change the loop bandwidth on the fly?

Yes! This is one of the greatest advantages of an ADPLL. In an analog PLL, the loop bandwidth is permanently hardwired by the physical capacitors soldered to the board. In an ADPLL, the loop filter is just code. If the system needs to lock onto a new frequency extremely fast, the processor can instantly widen the bandwidth by changing a line of code. Once locked, it can instantly narrow the bandwidth to filter out noise. This 'gear-shifting' is crucial for fast frequency-hopping systems.

Are ADPLLs better than Analog PLLs for everything?

No. While ADPLLs dominate low-cost, highly integrated consumer electronics (like Bluetooth, Wi-Fi, and 5G cellular modems), they still struggle in absolute high-end performance. The quantization noise of the digital components prevents them from matching the ultra-pure, ultra-low phase noise of a high-end analog synthesizer. For military radar or deep-space communications, analog PLLs are still required.

What is a Fractional-N ADPLL?

Just like analog PLLs, ADPLLs can be designed to lock to fractional multiples of the reference clock. They do this entirely in the digital domain by using a digital accumulator to keep track of the fractional phase accumulation. This allows the ADPLL to generate extremely precise frequencies that are not exact integer multiples of the crystal oscillator.

Related Terms

← Air Cavity Package Allan Variance →

System Design

ADPLL Quantization Simulator

Input your target oscillator frequency and the picosecond resolution of your Time-to-Digital Converter (TDC). Instantly calculate the resulting quantization noise floor and determine if your digital synthesizer will meet the strict EVM requirements of modern 5G modulations.

Calculate Digital Phase Noise