How does jitter limit ADC performance?

When an ADC samples a signal, timing uncertainty (jitter) on the sampling clock creates amplitude errors. For a sinusoidal input at frequency f_in with RMS jitter sigma_t: the amplitude error is proportional to the signal's slew rate times the timing error. SNR_jitter = -20*log10(2*pi*f_in*sigma_t). At f_in = 1 GHz, sigma_t = 100 fs: SNR = -20*log(2*pi*1e9*100e-15) = -20*log(6.28e-4) = 64 dB. This means: even a perfect 14-bit ADC (theoretical SNR = 86 dB) will be limited to 64 dB SNR by 100 fs jitter when sampling 1 GHz signals. For 5G NR direct RF sampling at 4 GHz, you need approximately 25 fs jitter for 12-bit performance.

What is the relationship between jitter and phase noise?

Jitter and phase noise are two representations of the same phenomenon. Phase noise L(f) is the frequency-domain view; jitter is the time-domain view. RMS jitter = 1/(2*pi*f0) * sqrt(2 * integral from f1 to f2 of L(f)*df), where L(f) is the single-sideband phase noise in dBc/Hz (converted to linear). The integration bandwidth [f1, f2] determines the jitter value. Wider integration = more jitter. For a clock with L(f) = -100 dBc/Hz at 10 kHz offset, -130 dBc/Hz at 100 kHz, -150 dBc/Hz at 1 MHz, integrated from 12 kHz to 20 MHz: the close-in phase noise (1/f^3 region) typically dominates the jitter integral.

What are the types of jitter?

Random jitter (RJ): Gaussian distribution, unbounded. Caused by thermal noise, shot noise in transistors. Characterized by RMS value. Deterministic jitter (DJ): bounded, repeatable. Subcategories: periodic jitter (PJ, caused by power supply coupling or crosstalk), data-dependent jitter (DDJ, caused by ISI), and duty-cycle distortion (DCD). Total jitter at BER: TJ = DJ_pp + 2*N*RJ_rms, where N is the number of sigma for the desired BER. At BER=1e-12: N=7.03, so TJ = DJ_pp + 14.07*RJ_rms. Period jitter: variation in one clock period. Cycle-to-cycle jitter: difference between consecutive periods. Time interval error (TIE): accumulated timing error over many cycles.

Timing & Clocking

Jitter

/jit-er/ (σ_t)

Jitter is timing edge deviation from ideal position. For ADCs: SNR_jitter = -20log(2πf_inσ_t). At 1 GHz input, 100 fs jitter limits SNR to 64 dB. Equivalent to phase noise in frequency domain. Types: random (Gaussian, unbounded), deterministic (bounded: periodic, data-dependent). Total jitter at BER=10^-12: TJ = DJ_pp + 14.07×RJ_rms.

1 GHz, 100fs: SNR=64 dB

ADC 5G: <25 fs needed

Phase noise: ~jitter

Understanding Jitter

Jitter is the invisible performance limiter in modern RF systems. As ADCs sample at ever-higher frequencies for direct RF sampling architectures, the sampling clock's jitter becomes the dominant SNR limitation. Even a perfect ADC with infinite resolution would be limited by jitter. The transition from IF sampling to direct RF sampling in 5G has driven clock jitter requirements from hundreds of femtoseconds down to sub-25 femtosecond levels.

Jitter Equations

RMS jitter:
σ_j = √(∫ L(f)·2sin²(πf/f₀)df) / (2πf₀)

Jitter from phase noise:
σ_j ≈ √(2∫L(f)df) / (2πf₀)

SNR limit from jitter:
SNR_max = −20log(2πf_inσ_j)

Jitter Requirements by Application

Application	RMS Jitter	f_in / f_clk	SNR Limit	Notes
Audio DAC	<1 ps	96 kHz	>120 dB	Easy requirement
IF sampling	200-500 fs	100-400 MHz	60-70 dB	Traditional Rx
5G NR sub-6	50-100 fs	1-4 GHz	64-72 dB	Direct RF sampling
5G NR mmWave	<25 fs	28-39 GHz IF	>70 dB	RFSoC clocking
Radar ADC	50-200 fs	1-10 GHz	60-75 dB	Wideband FMCW

Key Equations

Decibel conversion:
Power: dB = 10log(P₂/P₁)
Voltage: dB = 20log(V₂/V₁)

dBm to watts:
P(W) = 10^{(dBm−30)/10}
0 dBm = 1 mW, +30 dBm = 1 W

Wavelength:
λ = c/f = 300/f(MHz) meters

Comparison

Application	Jitter req	Frequency	SNR limit	Standard
12-bit ADC	<0.5 ps rms	1 GHz	62 dB	Data converter
10G Ethernet	<1.4 ps rms	10.3125 GHz	N/A	IEEE 802.3
SONET OC-48	<1 ps rms	2.488 GHz	N/A	Bellcore
PCIe Gen5	<0.5 ps rms	32 GHz	N/A	PCI-SIG
5G NR sync	<3 ns p-p	—	N/A	3GPP

Common Questions

Frequently Asked Questions

ADC limitation?

SNR = -20log(2*pi*f_in*sigma_t). 100 fs at 1 GHz: 64 dB. Even a perfect 14-bit ADC (86 dB) is limited to 64 dB by jitter. Direct RF sampling at 4 GHz needs ~25 fs for 12-bit performance.

Phase noise relation?

Same phenomenon, different domains. Jitter = time domain; phase noise = frequency domain. Integrate phase noise over bandwidth to get jitter. Close-in 1/f^3 noise dominates the integral. Low jitter requires low phase noise.

Types?

Random (RJ): Gaussian, unbounded, from thermal/shot noise. Deterministic (DJ): bounded, from power supply coupling, ISI. Total jitter at BER=1e-12: TJ = DJ_pp + 14.07*RJ_rms. Period and cycle-to-cycle jitter for clock quality.

Related Terms

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