A phase-locked loop is a feedback control system that forces a VCO output to track a stable reference in both frequency and phase. The PFD compares reference and feedback phases, the charge pump and loop filter generate the VCO tuning voltage, and the divider scales the VCO frequency down to the reference.

Signal Processing

Phase-Locked Loop

Q: Integer-N vs fractional-N?

Integer-N PLLs divide by whole numbers, so channel spacing equals the reference frequency. Simple but limited step size. Fractional-N PLLs use sigma-delta modulation to achieve fractional division ratios, enabling fine frequency steps with a higher reference frequency for faster lock and lower phase noise.

Q: What is loop bandwidth?

Loop bandwidth is the frequency at which the open-loop gain crosses 0 dB. It determines lock time, reference spur suppression, and VCO phase noise filtering. Wider bandwidth means faster lock but less spur suppression. Typically 1/10 to 1/20 of the reference frequency.

A phase-locked loop (PLL) is a negative-feedback control system that locks a VCO output to a stable reference in frequency and phase. Core blocks: phase-frequency detector (PFD), charge pump, loop filter, VCO, and programmable divider. PLLs are the foundation of integer-N and fractional-N frequency synthesizers in every modern RF transceiver.

Category: Signal Processing

Related to: VCO, PFD, Charge Pump, Synthesizer

Understanding Phase-Locked Loops

The PLL is arguably the most important subsystem in modern RF design. Every wireless transceiver, radar, signal generator, and clock recovery circuit depends on PLLs for frequency generation, modulation, and demodulation.

PLL Building Blocks

Reference oscillator: Crystal oscillator (TCXO, OCXO) providing the stable frequency reference
Phase-frequency detector (PFD): Compares reference and feedback signal edges, outputs UP/DOWN pulses proportional to phase error
Charge pump: Converts PFD pulses into current pulses that charge or discharge the loop filter
Loop filter: Low-pass filter that smooths charge pump output into VCO tuning voltage. Sets loop bandwidth and stability
VCO: Generates the output frequency controlled by the tuning voltage
Frequency divider (N): Divides VCO output by N so the PFD can compare it to the reference. f_out = N x f_ref

Architectures

Integer-N: Divides by whole numbers. Channel spacing = f_ref. Simple, low cost, but coarse step size or slow lock time
Fractional-N: Sigma-delta modulated divider achieves fractional division. Fine steps with high f_ref for fast lock and low noise
All-digital PLL (ADPLL): Replaces analog blocks with digital equivalents. Smaller die area, easier integration in advanced CMOS

Key Specifications

Loop bandwidth: Typically 1/10 to 1/20 of f_ref. Trades lock speed vs spur suppression
Lock time: Time to settle within specified frequency error after a channel change
Phase noise: In-band noise follows reference; out-of-band follows VCO
Reference spurs: Spurious tones at f_ref offset from the carrier. Suppressed by loop filter

Key Equations

PLL output:
f_out = N × f_ref/R

Loop bandwidth:
ω_n = √(K_PDK_VCO/(NC))

Phase noise (in-band):
PN_out = PN_ref + 20log(N)

Lock time (type II):
t_lock ≈ 2π×(5–10)/ω_n

Comparison

Type	Noise	Step size	Lock time	Use
Integer-N	20logN limited	f_ref	100–500 μs	Simple LO
Frac-N ΣΔ	Near-integer	f_ref/MOD	20–100 μs	Precision synth
ADPLL	DCO noise	Fine	5–50 μs	SoC integration
OPLL	Ultra-low	Continuous	10–100 μs	Coherent optical
Injection-locked	Lowest	Fixed ratio	<1 μs	Clock multiply

Common Questions

Frequently Asked Questions

What is a PLL?

A feedback control system that locks a VCO output to a stable reference in frequency and phase. PFD compares phases, charge pump and loop filter generate tuning voltage, divider scales VCO frequency to reference.

Integer-N vs fractional-N?

Integer-N divides by whole numbers; step size = f_ref. Fractional-N uses sigma-delta modulation for fractional ratios, enabling fine steps with higher f_ref for faster lock and lower phase noise.

What is loop bandwidth?

The frequency where open-loop gain crosses 0 dB. Determines lock time, spur suppression, and VCO noise filtering. Typically 1/10 to 1/20 of the reference frequency.

Related Terms

← Phase Linearity Phase Margin →