CMOS LNA Design
Understanding CMOS LNA Design
The Low Noise Amplifier (LNA) is the very first active component in a radio receiver, tasked with boosting microscopic antenna signals while adding as little thermal noise as physically possible. Historically, LNAs were built using exotic, expensive III-V compound semiconductors like Gallium Arsenide (GaAs) because standard Silicon was too slow and too noisy. CMOS LNA Design represents the industry's shift toward building these critical front-end components entirely in standard Silicon CMOS.
The driving force behind CMOS LNAs is not ultimate RF performance, but Integration. As Moore's Law shrank CMOS transistors to 65nm, 28nm, and below, their cutoff frequency (fT) skyrocketed past 100 GHz, making them fast enough for Wi-Fi and cellular frequencies. By designing the LNA in CMOS, it can be printed on the exact same piece of silicon as the digital modem, CPU, and memory, creating a true System-on-Chip (SoC) and reducing the cost of a smartphone radio to pennies.
Design Challenges in CMOS
Designing an LNA in CMOS is notoriously difficult. Silicon substrates are heavily conductive (lossy), meaning on-chip inductors have terrible Quality Factors (Q) and absorb RF energy, destroying the Noise Figure. Furthermore, CMOS transistors suffer from massive flicker noise (1/f noise), which bleeds into the lower RF bands. To combat this, CMOS LNAs heavily utilize the inductively-degenerated common-source topology, which uses a source inductor to simultaneously match the 50-ohm input impedance and tune out the gate-to-source capacitance without adding resistive thermal noise.
Where:
f = Operating RF frequency
fT = Cutoff frequency of the CMOS node (higher is better)
gm = Transconductance
Rg = Parasitic gate resistance (Must be minimized using multi-finger gate layouts)
Comparison
| Technology Node | Typical fT | Noise Figure @ 5GHz | Primary Application |
|---|---|---|---|
| 130nm CMOS | ~ 80 GHz | 2.5 - 3.5 dB | Legacy Bluetooth, Zigbee |
| 28nm CMOS | ~ 300 GHz | 1.2 - 2.0 dB | Modern Wi-Fi, 4G LTE SoCs |
| GaAs pHEMT (Discrete) | > 100 GHz | 0.3 - 0.8 dB | Deep Space, Military Radar, Cell Towers |
Frequently Asked Questions
Why are multi-finger layouts used in CMOS LNAs?
The physical polysilicon gate of a CMOS transistor has a surprisingly high electrical resistance (Rg). According to the noise equations, any resistance at the gate injects thermal noise directly into the signal path. By splitting a single massive transistor into 20 or 50 smaller parallel 'fingers', the gate resistance is divided down, drastically improving the Noise Figure.
What is an Inductively Degenerated Cascode?
It is the most popular CMOS LNA topology. A source inductor provides a noiseless 50-ohm real impedance match, the bottom transistor provides the low-noise amplification, and a top 'cascode' transistor shields the input from the output, neutralizing the Miller capacitance and stabilizing the amplifier at high frequencies.
Can a CMOS LNA survive without external filters?
Rarely. CMOS LNAs have very poor linearity and low breakdown voltages. If a strong out-of-band signal (like a nearby cell tower) hits a CMOS Wi-Fi LNA, it will instantly saturate and block the receiver. They almost always require external Surface Acoustic Wave (SAW) or Bulk Acoustic Wave (BAW) filters in front of them.