Why use bare die instead of packaged parts?

Three main reasons: (1) Lower parasitics: a QFN package adds 0.3-1 nH of lead inductance per pin. At 30 GHz, 0.5 nH represents 94 ohms of reactance, devastating for impedance matching. Bare die eliminates this entirely. (2) Smaller size: a 1x1 mm die in a 3x3 mm QFN wastes 89% of the area on package. In a multi-chip module with 10 bare dice, the size savings are enormous. (3) Better thermal: the die is soldered or epoxied directly to a metal substrate (AuSn eutectic at 280 C), providing thermal resistance under 5 C/W versus 20-50 C/W for plastic packages. This is why nearly all GaN PA modules for radar and 5G use bare die.

What is a Known Good Die (KGD)?

A Known Good Die is a bare die that has been fully tested and verified to meet specifications before it is sold or integrated into a module. Testing bare dice is challenging because they have no package pins to probe; test fixtures with probing needles or temporary carriers are required. Without KGD testing, a defective bare die discovered after assembly into a module wastes the entire module cost. KGD programs add 20-50% to the bare die cost but eliminate the risk of building expensive modules around bad chips. For GaAs and GaN MMIC die, KGD testing includes S-parameter measurements, power and efficiency testing, and DC parameter verification.

How are bare dice attached?

Three main methods: (1) Wire bonding: the die is epoxied face-up (cavity-up) and gold or aluminum wires connect the bond pads to the substrate traces. Most common for MMIC and RF die below 40 GHz. Wire bonds add 0.2-0.5 nH each. (2) Flip-chip: the die is flipped face-down and solder bumps or gold stud bumps connect directly to the substrate pads. Eliminates wire bond inductance, enabling operation to 100+ GHz. Used in advanced 5G modules. (3) Embedded die: the die is placed inside the PCB substrate itself (embedded in the laminate layers), with connections made through micro-vias. Emerging for ultra-compact SiP designs.

Semiconductor Packaging

Bare Die

/bair dy/ (naked die, chip-on-board)

A Bare Die is an unpackaged semiconductor chip mounted directly into a hybrid circuit, multi-chip module (MCM), or system-in-package (SiP). Eliminating the package removes lead inductance and capacitance parasitics, reduces size by 5-10x, and improves thermal dissipation through direct die-attach. Nearly all GaN PA modules for radar and 5G base stations use bare MMIC die for these advantages.

Category: Semiconductor Packaging

Attach: Wire bond, flip-chip, embedded

Advantage: Lowest parasitics

Understanding Bare Die

At microwave and millimeter-wave frequencies, package parasitics dominate performance. A typical QFN package adds 0.3-1 nH per pin, which at 30 GHz represents nearly 100 ohms of reactance. This makes impedance matching extremely difficult and limits the usable frequency range. Bare die integration eliminates these parasitics entirely, which is why the highest-performance RF modules (radar transmit/receive modules, 5G massive MIMO power amplifiers, satellite transponders) use bare MMIC die assembled on low-loss substrates like alumina, AlN, or LTCC.

Parasitic Comparison

Bare Die:
A Bare Die is an unpackaged semiconductor chip mounted directly into a hybrid circuit, multi-chip module (MCM), or system-in-package (SiP). Eliminating the package removes lead...

Key specifications:
30 GHz | 100 ohm | 10 GHz | 77 GHz

Power: P(dBm) = 10log(P_mW), 0dBm = 1mW

Die Attach Method Comparison

Method	Inductance	Frequency	Cost	Rework	Application
Wire bond (Au)	0.2-0.5 nH	<40 GHz	Low	Possible	MMIC modules, hybrids
Wire bond (Al)	0.3-0.7 nH	<20 GHz	Lowest	Possible	Power amps, low freq
Flip-chip (solder)	0.01-0.05 nH	<100+ GHz	Medium	Difficult	5G, mmWave, SiP
Flip-chip (Au stud)	0.02-0.1 nH	<80 GHz	Medium	Moderate	Research, prototyping
Embedded die	<0.05 nH	<100+ GHz	High	None	Ultra-compact SiP

Key Equations

Noise Figure cascade (Friis):
NF_total = NF₁ + (NF₂−1)/G₁ + (NF₃−1)/(G₁G₂)

Gain (dB):
G = 10log(P_out/P_in) = 20log(V_out/V_in)

IP3 & dynamic range:
SFDR = 2/3(IIP3 − NF − 10log(kTB)) dB

Comparison

Aspect	Bare Die Spec	Typical Range	Impact	Design Note
Primary function	A Bare Die is an unpackaged semiconducto...	Application-dep.	Critical	Verify in sim
Operating range	Eliminating the package removes lead ind...	Application-dep.	Critical	Verify in sim
Performance	Nearly all GaN PA modules for radar and...	Application-dep.	Critical	Verify in sim
Integration	Understanding Bare Die At microwave and...	Application-dep.	Critical	Verify in sim
Trade-off	A typical QFN package adds 0.3-1 nH per...	Application-dep.	Critical	Verify in sim

Common Questions

Frequently Asked Questions

Why use bare die?

Lower parasitics (no package inductance). 5-10x smaller. Better thermal (direct die-attach: 2-5 C/W vs. 20-50 C/W for QFN). At 30 GHz, 0.5 nH of package inductance = 94 ohms reactance. Nearly all GaN PA modules for radar and 5G use bare die.

What is Known Good Die?

Bare die fully tested before integration. Testing without package is challenging (requires probing fixtures). KGD adds 20-50% cost but avoids wasting expensive module on bad chip. Includes S-parameters, power/efficiency, and DC verification for MMIC die.

How are dice attached?

Wire bonding (face-up, Au/Al wires, 0.2-0.5 nH each, <40 GHz). Flip-chip (face-down, solder/Au bumps, <0.05 nH, 100+ GHz). Embedded die (inside PCB laminate, micro-via connections, ultra-compact SiP). Wire bond most common; flip-chip for highest frequency.

Related Terms

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