Semiconductor Packaging

Back-Grinding

Q: Why do GaN MMICs need back-grinding?

GaN MMICs are fabricated on SiC substrates that start at 400-500 micrometers thick. The SiC must be thinned to about 100 micrometers to etch via holes through the substrate for ground connections. These substrate vias provide the low-inductance ground path that GaN power amplifiers require for stable operation. Without them, wire bonds to the ground plane would add too much inductance at mmWave frequencies, degrading gain and potentially causing oscillation. Back-grinding SiC is particularly challenging because SiC has a Mohs hardness of 9 (nearly diamond), requiring diamond grinding wheels.

Q: What is the difference between back-grinding and back-lapping?

Back-grinding uses a rotating diamond wheel to rapidly remove material, thinning a wafer from 750 to 200 micrometers in minutes. It leaves subsurface damage (microcracks) in a layer about 5-10 micrometers deep. Back-lapping (or polishing) uses a slurry of fine abrasive particles on a rotating pad to slowly remove material with minimal damage. Many RF processes use grinding for bulk removal followed by a CMP (chemical-mechanical polishing) step to eliminate the damage layer and achieve a smooth, crack-free surface that won't propagate fractures during dicing and die attach.

Q: How thin can wafers be ground for RF applications?

Standard thickness for RF ICs is 100-150 micrometers for GaAs and GaN MMICs, which balances via hole aspect ratio against mechanical handling concerns. For TSV (through-silicon via) applications in CMOS-based RF ICs, wafers are ground to 50-75 micrometers. Some advanced fan-out wafer-level packaging processes thin to 30 micrometers. Below about 50 micrometers, the wafer becomes extremely fragile and requires specialized handling equipment with vacuum chucks and reinforced tape frames. GaAs is particularly brittle due to its zinc blende crystal structure.

/bak grynd-ing/

Back-grinding is a wafer thinning process that mechanically grinds the back surface of a processed semiconductor wafer to reduce die thickness from the standard 725-775 micrometers down to 50-200 micrometers. In RF and mmWave IC manufacturing, thinning enables through-substrate via formation for low-inductance grounding, reduces thermal resistance from junction to heat sink, and allows thinner packages for space-constrained applications like phased array modules.

Category: Semiconductor Packaging

Typical Target: 100-150 μm (GaAs/GaN)

Removal Rate: 2-5 μm/sec

Understanding Back-Grinding

Semiconductor wafers are manufactured thick (725-775 micrometers for 200mm wafers, 775 micrometers for 300mm) for mechanical strength during front-end processing. All the transistors and BEOL interconnects occupy only the top 10-15 micrometers. The remaining 700+ micrometers of substrate is dead weight that adds thermal resistance, prevents via hole formation, and wastes vertical space in the final package.

For RF MMICs, particularly GaAs and GaN devices, the standard final thickness is 100 micrometers (4 mils). This allows via holes to be etched through the substrate with a manageable aspect ratio, providing low-inductance ground connections that are essential for stable power amplifier operation above 10 GHz.

Thermal Impact of Thinning

Back-Grinding:
Back-grinding is a wafer thinning process that mechanically grinds the back surface of a processed semiconductor wafer to reduce die thickness from the standard 725-775...

Key specifications:
-775 m | -200 m | 200 mm | 775 m | 300 mm

Power: P(dBm) = 10log(P_mW), 0dBm = 1mW

Thinning Targets by Substrate

Substrate	Starting	Target	Via Diameter	Challenge
GaAs	625 μm	100 μm	50-80 μm	Brittle, cleavage along crystal planes
GaN/SiC	400 μm	100 μm	40-60 μm	SiC hardness (Mohs 9), slow grinding
Si (CMOS)	775 μm	50-200 μm	5-10 μm (TSV)	Stress-induced warpage at < 100 μm
InP	350 μm	75 μm	30-50 μm	Very brittle, expensive substrate
Si (RF SOI)	725 μm	200 μm	N/A (no vias)	Package height constraint only

Key Equations

Noise Figure cascade (Friis):
NF_total = NF₁ + (NF₂−1)/G₁ + (NF₃−1)/(G₁G₂)

Gain (dB):
G = 10log(P_out/P_in) = 20log(V_out/V_in)

IP3 & dynamic range:
SFDR = 2/3(IIP3 − NF − 10log(kTB)) dB

Comparison

Aspect	Back-Grinding Spec	Typical Range	Impact	Design Note
Primary function	Understanding Back-Grinding Semiconducto...	Application-dep.	Critical	Verify in sim
Operating range	All the transistors and BEOL interconnec...	Application-dep.	Critical	Verify in sim
Performance	The remaining 700+ micrometers of substr...	Application-dep.	Critical	Verify in sim
Integration	For RF MMICs, particularly GaAs and GaN...	Application-dep.	Critical	Verify in sim
Trade-off	Critical Verify in sim Operating range A...	Application-dep.	Critical	Verify in sim

Common Questions

Frequently Asked Questions

Why do GaN MMICs need back-grinding?

GaN on SiC substrates start at 400-500 micrometers. The SiC must be thinned to ~100 micrometers to etch via holes for ground connections. These substrate vias provide the low-inductance ground path that power amplifiers require for stable mmWave operation. Without them, wire bonds add too much inductance, degrading gain and risking oscillation. SiC grinding is challenging because SiC has Mohs hardness of 9, requiring diamond grinding wheels.

What is the difference between back-grinding and back-lapping?

Grinding uses a diamond wheel for rapid bulk removal (750 to 200 micrometers in minutes) but leaves subsurface damage 5-10 micrometers deep. Lapping uses fine abrasive slurry for slow, damage-free removal. Most RF processes use grinding for bulk removal followed by CMP polishing to eliminate the damage layer and prevent fracture during dicing.

How thin can wafers be ground for RF applications?

Standard is 100-150 micrometers for GaAs/GaN MMICs. TSV applications in CMOS go to 50-75 micrometers. Some fan-out processes thin to 30 micrometers. Below 50 micrometers, wafers require vacuum chucks and reinforced tape frames. GaAs is particularly fragile due to its zinc blende crystal structure.

Related Terms

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