What materials are used in modern BEOL stacks?

Modern BEOL uses copper (Cu) for metal lines (replacing the older aluminum process) because copper has 40% lower resistivity (1.7 vs. 2.65 micro-ohm-cm). Inter-metal dielectrics have evolved from SiO2 (k=4.0) to low-k materials like SiCOH (k=2.5-3.0) and ultra-low-k porous variants (k=2.0-2.5) to reduce parasitic capacitance between adjacent metal lines. Barrier metals like TaN and Ta prevent copper from diffusing into the dielectric. The top metal layer is often aluminum for wire bonding compatibility. Advanced RF processes add thick top metals (3-4 micrometers) specifically for low-loss inductors and transmission lines.

Semiconductor Fabrication

Back-End of Line (BEOL)

Q: Why does BEOL matter more at mmWave frequencies?

At sub-6 GHz frequencies, transistor performance (fT, fmax) usually dominates IC behavior and BEOL parasitics are a secondary concern. At mmWave (28 GHz, 39 GHz, 77 GHz), the interconnect parasitics become comparable to or larger than the transistor impedances. A 50 femtofarad parasitic capacitance from a metal crossing is negligible at 2 GHz but presents an impedance of only 57 ohms at 56 GHz, significantly loading the signal path. Interconnect resistance also matters: at 28 nm CMOS, the thinnest metal layers have sheet resistance of 1 to 2 ohms per square, adding non-trivial series loss to mmWave matching networks built in BEOL.

Q: What is the difference between FEOL and BEOL?

FEOL (Front-End of Line) creates the active devices: transistors, diodes, and resistors formed in and on the silicon (or GaN, SiGe, InP) substrate. FEOL involves ion implantation, gate oxide growth, gate patterning, and source/drain formation. BEOL starts after the transistors are complete and builds the metal wiring stack that connects everything together. FEOL determines the transistor's fT and fmax. BEOL determines how much of that intrinsic performance actually reaches the circuit's external ports after interconnect losses.

/bak-end/ or /bee-ee-oh-ell/

The Back-End of Line (BEOL) is the semiconductor fabrication phase that follows transistor formation and builds the metal interconnect stack: copper or aluminum wiring layers, inter-metal dielectric (IMD) films, vias connecting different metal levels, and the final passivation layer. For RF and mmWave ICs, BEOL quality directly determines parasitic capacitance between signal lines, series resistance losses in matching networks, and the Q-factor of on-chip inductors.

Category: Semiconductor Fabrication

Metal Layers: 6 to 15 (advanced CMOS)

Key Materials: Cu, low-k SiCOH, TaN

Understanding BEOL

A transistor by itself is useless. It becomes part of a circuit only when metal wires connect its gate, drain, and source to other transistors, passive components, and external bond pads. The BEOL process builds this wiring infrastructure, layer by layer, from the transistor contacts up through the final pad metallization. In a modern 7 nm CMOS process, there can be 13 or more metal layers, each with specific width and spacing rules optimized for different functions: thin lower metals for dense digital routing, thick upper metals for power distribution and RF inductors.

RF Impact of BEOL Parasitics

Back-End of Line (BEOL):
The Back-End of Line (BEOL) is the semiconductor fabrication phase that follows transistor formation and builds the metal interconnect stack: copper or aluminum wiring layers,...

Key specifications:
7 nm | -15 a | 5 GHz | -10 a | 28 GHz

Power: P(dBm) = 10log(P_mW), 0dBm = 1mW

BEOL Metal Stack Comparison

Process	Metal Layers	Top Metal	IMD k-value	RF Application
GF 45nm SOI	10 Cu + 1 Al	4 μm Al	2.7 (SiCOH)	mmWave 5G, radar
TSMC 16nm FinFET	12 Cu + 1 Al	3.4 μm Al	2.5-3.0	Sub-6 GHz 5G FEM
TSMC 7nm	13 Cu	3 μm Cu	2.55	mmWave beamformer
GaN on SiC (0.25 μm)	2 Au	5 μm Au	SiN (6.8)	Power amplifier MMIC
InP HBT (0.5 μm)	3-4 Au	3 μm Au	BCB (2.65)	E-band transceiver

Key Equations

Noise Figure cascade (Friis):
NF_total = NF₁ + (NF₂−1)/G₁ + (NF₃−1)/(G₁G₂)

Gain (dB):
G = 10log(P_out/P_in) = 20log(V_out/V_in)

IP3 & dynamic range:
SFDR = 2/3(IIP3 − NF − 10log(kTB)) dB

Comparison

Aspect	Back-End of Line (BEOL) Spec	Typical Range	Impact	Design Note
Primary function	For RF and mmWave ICs, BEOL quality dire...	Application-dep.	Critical	Verify in sim
Operating range	Understanding BEOL A transistor by itsel...	Application-dep.	Critical	Verify in sim
Performance	It becomes part of a circuit only when m...	Application-dep.	Critical	Verify in sim
Integration	The BEOL process builds this wiring infr...	Application-dep.	Critical	Verify in sim
Trade-off	Critical Verify in sim Operating range U...	Application-dep.	Critical	Verify in sim

Common Questions

Frequently Asked Questions

Why does BEOL matter more at mmWave frequencies?

At sub-6 GHz, transistor performance dominates and BEOL parasitics are secondary. At mmWave (28-77 GHz), interconnect parasitics become comparable to transistor impedances. A 50 fF parasitic from a metal crossing presents only 57 ohms at 56 GHz, significantly loading the signal path. Interconnect resistance also adds series loss to mmWave matching networks built in BEOL.

What is the difference between FEOL and BEOL?

FEOL creates active devices (transistors, diodes) in the substrate through implantation, gate formation, and source/drain processing. BEOL builds the metal wiring stack that connects everything. FEOL determines the transistor's fT and fmax. BEOL determines how much of that intrinsic performance reaches the circuit's external ports after interconnect losses.

What materials are used in modern BEOL?

Copper (40% lower resistivity than aluminum) for metal lines. Low-k SiCOH (k=2.5-3.0) and ultra-low-k porous variants (k=2.0-2.5) for inter-metal dielectrics. TaN/Ta barrier metals prevent copper diffusion. Advanced RF processes add thick top metals (3-4 micrometers) for low-loss inductors and transmission lines.

Related Terms

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