What are the advantages of MMICs over discrete circuits?

Size: MMIC integrates matching networks, bias circuits, and multiple stages on a 1-5mm die. Equivalent discrete circuit might occupy 10-50x more PCB area. Reproducibility: all components are lithographically defined. Part-to-part variation is much lower than discrete designs with hand-tuned matching. Frequency: at mmWave frequencies (>30 GHz), discrete components become impractical. Bond wire inductance, PCB trace parasitics, and component tolerances are too large. MMICs use on-chip transmission lines and thin-film elements with precise control. Reliability: fewer solder joints and wire bonds. All connections are on-chip. Cost at volume: once the mask set is paid for, per-chip cost can be very low ($0.10-$10 depending on die size and technology). However, NRE (mask set + design) is $100K-$1M.

What are the main MMIC technologies?

GaAs pHEMT (0.15-0.25 um): DC-110 GHz. Lowest noise (LNA), moderate power. Most mature MMIC technology. Foundries: WIN, TriQuint/Qorvo, OMMIC, UMS. GaAs HBT (1-3 um): DC-40 GHz. Best for PAs below 6 GHz (smartphone PAs), VCOs, and gain blocks. Skyworks, Qorvo dominate. GaN HEMT (0.15-0.25 um): DC-40 GHz. Highest power density (5-10 W/mm). Radar, EW, 5G BS PAs. Foundries: Wolfspeed, Qorvo, WIN. SiGe BiCMOS (0.13 um, 55 nm): DC-100 GHz. Good NF, excellent linearity, low cost. Integration with CMOS digital. Used for automotive radar, 5G mmWave, test equipment. InP HEMT (35-100 nm): DC-700 GHz. Lowest noise at mmWave and sub-THz. Radio astronomy and scientific instruments.

What is the difference between bare die and packaged MMICs?

Bare die: the unpackaged semiconductor chip. Must be wire-bonded or flip-chip attached to the circuit. Advantages: smallest size, lowest parasitic inductance (critical above 30 GHz), lowest cost per unit. Disadvantages: requires die attach and wire bonding capability, more difficult to handle and test, sensitive to ESD and contamination. Packaged: die mounted in a QFN, LCC, or connectorized housing with gold bond wires to package leads. Advantages: easy to handle and solder, pre-tested, ESD protection, standard footprint. Disadvantages: package parasitics limit frequency (QFN typically good to 20 GHz, some to 40 GHz), larger size, higher cost. For mmWave (>40 GHz): bare die or wafer-level packaging (fan-out, embedded die) is almost always required.

Semiconductor Technology

MMIC (Monolithic Microwave IC)

/mim-ik/

An MMIC is a complete RF function on a single semiconductor die: amplifier, mixer, oscillator, switch, or multi-function. GaAs pHEMT: DC-110 GHz, lowest noise. GaN HEMT: highest power. SiGe: low cost, high integration. InP: sub-THz. Die sizes 1-5 mm. Integrates matching networks, bias, and transmission lines. Bare die for mmWave; QFN packages for sub-20 GHz.

GaAs: DC-110 GHz

Die size: 1-5 mm

GaN: 5-10 W/mm

Understanding MMICs

The MMIC revolutionized microwave engineering by bringing the integration and reproducibility of silicon ICs to the RF world. Before MMICs, microwave circuits were built from discrete transistors, hand-soldered components, and tuned cavities, each one slightly different. MMICs deliver consistent, repeatable performance from chip to chip, enabling mass production of complex microwave systems. Today, everything from smartphone PAs to satellite transponders to radar transmitters relies on MMIC technology.

MMIC Design Elements

MMIC (Monolithic Microwave IC):
Substrate: GaAs, InP, GaN, SiGe
Transmission lines on chip
Frequency: 1–300+ GHz

Typical elements:
FET, HEMT, HBT, MIM cap, spiral inductor
Thin-film resistor (NiCr, TaN)

Substrate thickness:
50–100 μm (thinned for via/heat)
ε_r: GaAs = 12.9, InP = 12.4

MMIC Technology Comparison

Technology	f_max	Power Density	NF_min	Cost	Application
GaAs pHEMT	200 GHz	0.8-1.5 W/mm	0.3 dB	Moderate	LNA, switch, mixer
GaAs HBT	100 GHz	1-2 W/mm	2-4 dB	Moderate	Phone PA, VCO
GaN HEMT	100 GHz	5-10 W/mm	0.5-2 dB	High	Radar PA, 5G BS
SiGe BiCMOS	300 GHz	0.3 W/mm	0.8-2 dB	Low	Auto radar, 5G
InP HEMT	700 GHz	0.3 W/mm	0.1 dB	Very high	THz, astronomy

Key Equations

Noise Figure cascade (Friis):
NF_total = NF₁ + (NF₂−1)/G₁ + (NF₃−1)/(G₁G₂)

Gain (dB):
G = 10log(P_out/P_in) = 20log(V_out/V_in)

IP3 & dynamic range:
SFDR = 2/3(IIP3 − NF − 10log(kTB)) dB

Comparison

Technology	f_max	NF	P_out	Application
GaAs pHEMT	100 GHz	0.5–1 dB	0.5 W/mm	LNA, switch
GaN HEMT	40 GHz	1–2 dB	5–10 W/mm	PA, T/R module
InP HEMT	300+ GHz	0.3 dB	0.1 W/mm	mmW LNA
SiGe HBT	300 GHz	1–3 dB	Low	High-integration
CMOS (SOI)	100 GHz	3–5 dB	0.1 W/mm	5G/WiFi mass mkt

Common Questions

Frequently Asked Questions

vs. discrete?

10-50x smaller. Lithographically defined = reproducible. Essential above 30 GHz (discrete parasitics too large). Cost: NRE $100K-1M but per-chip $0.10-10. Fewer solder joints = higher reliability.

Technologies?

GaAs pHEMT: LNA/switch, DC-110 GHz. GaAs HBT: phone PA, DC-40 GHz. GaN: high-power, 5-10 W/mm. SiGe: low cost, auto radar. InP: sub-THz. Each optimized for different applications.

Bare die vs. packaged?

Bare die: smallest, lowest parasitics, needed above 40 GHz. Requires wire bonding. Packaged (QFN): easy handling, pre-tested, ESD protection, good to ~20-40 GHz. Package parasitics limit high-freq performance.

Related Terms

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