How close should bypass capacitors be to IC power pins?

For RF circuits operating above 1 GHz, bypass capacitors must be within 1-2 mm of the IC power pin. Every millimeter of trace adds approximately 0.7-1.0 nH of parasitic inductance, and at 2 GHz, just 1 nH presents 12.6 ohms of impedance. The ground via should be placed directly adjacent to the capacitor's ground pad, not routed through a trace. For BGA packages, place bypass capacitors on the opposite side of the board directly beneath the power ball with a shared via fence. At frequencies below 500 MHz, 5-10 mm distances are acceptable because the wavelength is long enough that trace inductance has minimal impact.

How many bypass capacitors should I use per power pin?

The number depends on the bandwidth of noise you need to suppress. A single 100 nF capacitor covers approximately 1 MHz to 200 MHz. For broadband decoupling from 100 kHz to 2 GHz, use three capacitors: 10 uF (bulk), 100 nF (mid-band), and 10-100 pF (RF band). High-pin-count FPGAs and SoCs with dozens of VDD pins may need 50-100 total bypass capacitors. IC datasheets and reference designs specify the recommended bypass network; always follow the manufacturer's recommendation as the starting point, then refine based on power integrity simulation if emissions testing reveals problems.

Should I use C0G or X7R dielectric for RF bypass?

C0G (also called NP0) is preferred for RF bypass because it has zero DC bias voltage derating, zero temperature coefficient, very low ESR, and no piezoelectric effects. X7R loses up to 80% of its capacitance under DC bias (a 100 nF X7R 0402 at 3.3V may only provide 30-50 nF effective capacitance) and has higher ESR. However, C0G is only available in small values (typically up to 10 nF in 0402 packages), so X7R or X5R remains necessary for bulk capacitance above 100 nF. The practical approach: use C0G for the small high-frequency bypass caps closest to the IC, and X7R/X5R for the larger mid-band and bulk capacitors further from the pin.

What are Bypass Guidelines? | PCB Decoupling Best Practices

Definition & Scope

Bypass guidelines are a structured set of design rules that govern how decoupling capacitors are selected, placed, and connected on a printed circuit board to maintain low power supply impedance across the frequency range of interest. These guidelines address four interrelated concerns: capacitor value and dielectric selection (determining the frequency range of effective bypassing), PCB placement distance (controlling parasitic inductance), via and ground plane design (minimizing return current path impedance), and multi-capacitor staging (ensuring broadband coverage without anti-resonance problems).

In RF and mixed-signal designs, bypass guidelines are not optional suggestions but mandatory design constraints. A PLL with a supply impedance specification of less than 100 milliohms at 10 MHz requires specific bypass capacitor values and placement tolerances to meet that target. An LNA with -174 dBm/Hz input-referred noise cannot tolerate 10 mV of supply ripple without degrading its noise figure. IC manufacturers publish bypass guidelines in their datasheets and application notes, and experienced RF designers extend those guidelines with additional rules learned from failed EMC tests and degraded receiver sensitivity.

Key Design Rules

Maximum trace length to IC pin:

L_max = Z_target / (2π × f_max × L_per-mm)

Z_target = 1 Ω, f_max = 2 GHz, L/mm = 0.8 nH: L_max = 0.1 mm (impractical; use 0201 on-pad)

Via inductance:

L_via ≈ 0.2 nH per 0.1 mm of via height (in 0.3 mm drill)

1.6 mm board: L_via ≈ 3.2 nH (use multiple vias in parallel)

Ground plane slot impedance:

Z_slot ≈ j × 2πf × L_slot where L_slot ≈ 0.5 nH per mm of slot length

Bypass Guideline Summary

Rule	Sub-1 GHz Design	1-6 GHz RF	>6 GHz mmWave
Max distance to pin	<5 mm	<2 mm	<0.5 mm (on-pad)
Smallest cap dielectric	X7R acceptable	C0G required	C0G, 0201 only
Ground vias per cap	1 minimum	2 recommended	4+ via fence
Staging levels	2 (bulk + bypass)	3 (bulk + mid + RF)	3-4 + on-die
Supply Z target	<1 Ω	<0.5 Ω	<0.2 Ω
Ground plane	Solid, no splits	Continuous under IC	Full copper pour

Practical Application

An X-band (10 GHz) radar receiver front-end module uses a GaAs LNA die mounted on a 10-mil Rogers RO4003C substrate. The VDD pin requires supply impedance below 0.3 ohms from DC to 15 GHz. The bypass network consists of a 4.7 uF X5R 0805 tantalum capacitor at the module power entry (effective DC to 5 MHz), a 100 nF C0G 0402 capacitor 3 mm from the die (effective 5-300 MHz), a 10 pF C0G 0201 capacitor placed 0.5 mm from the bond pad (effective 300 MHz-3 GHz), and a 0.5 pF on-die MIM capacitor integrated into the MMIC (effective 3-20 GHz). Each stage hands off to the next at its SRF, maintaining continuous low impedance. The ground vias use a four-via fence pattern around each small capacitor to minimize via inductance to 0.15 nH total.

Frequently Asked Questions

How close to the IC pin?

Within 1-2 mm for RF above 1 GHz. Every mm adds ~1 nH (12.6 ohms at 2 GHz). For BGA, place caps on the board underside beneath the power ball with shared via fence. Below 500 MHz, 5-10 mm is acceptable.

How many caps per power pin?

Single 100 nF covers 1-200 MHz. Broadband (100 kHz-2 GHz): three caps (10 uF + 100 nF + 10-100 pF). High-pin-count FPGAs may need 50-100 total. Always start from the IC datasheet recommendation.

C0G or X7R for RF bypass?

C0G (NP0) for RF: zero DC bias derating, stable, low ESR. X7R loses 50-80% capacitance under DC bias. Use C0G for the small caps closest to the IC pin; X7R/X5R for bulk capacitance above 100 nF further from the pin.

Bypass Guidelines