Bulk Decoupling

Large-value capacitors for low-frequency power rail energy storage and filtering

Definition & Role in PDN

Bulk decoupling is the practice of placing large-value capacitors (10-100+ µF) near the power supply entry point or voltage regulator output on an RF PCB to provide low-frequency energy storage and filtering. These capacitors serve as a local charge reservoir that supplies transient current demands before the voltage regulator can respond, preventing voltage droops that would modulate the RF circuit's operating point and degrade performance.

In the power distribution network (PDN) impedance profile, bulk decoupling capacitors dominate the impedance from DC to approximately 1 MHz, while local bypass capacitors (100 nF MLCC at each IC pin) cover 1 MHz to 1 GHz. The combined PDN must maintain impedance below the target Ztarget = ΔVmax/Itransient across the entire frequency range. For a sensitive RF IC drawing 500 mA with 50 mV tolerance, Ztarget = 100 mΩ, requiring careful selection of bulk capacitor values, ESR, ESL, and PCB plane geometry.

Key Formulas

Minimum Bulk Capacitance:

Cbulk = Itransient × tresponse / ΔVmax

2 A pulse, 1 µs, 100 mV droop: C = 20 µF (use 47-100 µF with margin)

Self-Resonant Frequency:

SRF = 1 / (2π√(LESL × C))

100 µF, 5 nH ESL: SRF = 225 kHz | 100 nF, 0.5 nH: SRF = 22 MHz

Target PDN Impedance:

Ztarget = ΔVmax / Itransient

Decoupling Capacitor Comparison

ParameterBulk ElectrolyticBulk TantalumBulk MLCCLocal Bypass MLCC
Capacitance10-1000 µF10-100 µF10-100 µF10-100 nF
ESR50-500 mΩ20-200 mΩ2-10 mΩ5-50 mΩ
ESL5-15 nH2-5 nH0.5-2 nH0.3-1 nH
SRF (typical)50-500 kHz200 kHz-2 MHz1-5 MHz20-200 MHz
Effective RangeDC-100 kHzDC-1 MHzDC-5 MHz1 MHz-1 GHz
PlacementNear regulatorNear regulatorNear regulatorAt IC power pin
Size (typ.)Large (can)Medium (SMD)Medium (1210)Small (0402)

Practical Application

A pulsed S-band radar transmitter module draws 8 A from a 28 V rail during the 10 µs transmit pulse at 10% duty cycle. The GaN PA's drain voltage must remain within ±100 mV during the pulse. Bulk decoupling requires C = 8 × 10µs / 0.1 = 800 µF minimum. The design uses four 330 µF tantalum capacitors (total 1320 µF) with 30 mΩ parallel ESR, supplemented by ten 10 µF X7R MLCCs for mid-frequency decoupling and twenty 100 nF C0G MLCCs at each PA drain pin. The PDN impedance simulation confirms Z < 12.5 mΩ (100 mV / 8 A) from DC to 100 MHz, ensuring the PA drain voltage remains stable throughout each pulse.

Frequently Asked Questions

Bulk decoupling vs local bypass?

Bulk: large caps (10-100 µF) near regulator for DC-1 MHz. Local bypass: small caps (10-100 nF) at each IC pin for 1 MHz-1 GHz. Both needed because bulk caps have too much ESL for high frequencies, and small caps lack energy storage for sustained demands.

How to calculate bulk capacitance?

C = Itransient × tresponse / ΔVmax. For 2 A, 1 µs, 100 mV: C = 20 µF. Use 2-3× margin. ESR must satisfy I × ESR < ΔVmax.

Why does ESL matter?

ESL sets the self-resonant frequency: SRF = 1/(2π√(LC)). Above SRF, the cap becomes inductive and ineffective. 100 µF electrolytic: SRF ~225 kHz. 100 nF ceramic: SRF ~22 MHz. Multiple values are paralleled to cover all frequency decades.