Why not just build an oscillator at the desired frequency?

Above about 30 GHz, building a stable, low-phase-noise oscillator becomes extremely difficult because transistor gain drops off, resonator Q decreases, and parasitic effects dominate. A better approach is to build a high-quality oscillator at a lower frequency (where Q is high and stability is good) and multiply up. A 10 GHz DRO with minus 120 dBc/Hz phase noise at 10 kHz offset, tripled to 30 GHz, becomes minus 110.5 dBc/Hz (phase noise increases by 20 log10(N) = 9.5 dB for N=3). This is still much better than a 30 GHz free-running VCO, which might achieve only minus 90 dBc/Hz. At frequencies above 100 GHz, multiplication is often the only practical approach.

What is the conversion efficiency of a frequency multiplier?

Conversion loss (output power divided by input power) depends on the multiplication factor and the nonlinear device. Passive diode doublers: 6 to 10 dB conversion loss. Passive diode triplers: 10 to 15 dB. Active transistor doublers: 0 to 5 dB conversion loss (or even slight gain). Active triplers: 5 to 10 dB loss. The theoretical minimum conversion loss for a resistive multiplier is 1/N squared times some correction factors, but practical devices include output filter losses and impedance matching losses. Higher multiplication factors (x5, x6) are increasingly inefficient and are better achieved by cascading a doubler and a tripler.

How does multiplication affect phase noise?

Phase noise increases by 20 log10(N) dB, where N is the multiplication factor. Doubling adds 6 dB. Tripling adds 9.5 dB. A cascade of doubler plus tripler (x6 total) adds 15.6 dB. This is because the phase fluctuations of the input are multiplied along with the frequency. A 10 GHz source at minus 120 dBc/Hz, multiplied by 6 to 60 GHz, becomes minus 104.4 dBc/Hz. This degradation is unavoidable and is the primary trade-off of the multiplication approach. To minimize the impact, start with the lowest possible phase noise at the base frequency.

Active Components

Frequency Multiplier

Building a stable oscillator at 300 GHz is nearly impossible. But a stable 10 GHz dielectric resonator oscillator is routine. Drive it into a tripler to get 30 GHz. Triple again to reach 90 GHz. Double that for 180 GHz. One more doubler yields 360 GHz. Four simple nonlinear stages, each followed by a bandpass filter to select the desired harmonic and reject everything else, can reach sub-terahertz frequencies from a well-characterized 10 GHz source. The phase noise degrades by 20·log(N) for each multiplication stage, but the result is still vastly better than any direct oscillator at that frequency. This is how most mmWave and THz sources are built today.

Category: Active Components

Output: f_out = N × f_in

PN Penalty: 20·log(N) dB

Multiplier Types and Performance

Type	Factor	Conversion	Output Freq.	Power Out	Technology
Active doubler (MMIC)	×2	−2 to +3 dB	to 60 GHz	+10 to +15 dBm	GaAs, InP, SiGe
Passive diode doubler	×2	−6 to −10 dB	to 300 GHz	0 to +5 dBm	GaAs Schottky
Active tripler (MMIC)	×3	−5 to −10 dB	to 40 GHz	+5 to +10 dBm	GaAs, InP
Passive diode tripler	×3	−10 to −15 dB	to 600 GHz	−5 to 0 dBm	GaAs Schottky
Varactor doubler	×2	−3 to −6 dB	to 100 GHz	+5 to +10 dBm	GaAs varactor

Phase noise degradation:
L_out(f_m) = L_in(f_m) + 20·log₁₀(N) dB

Example: 10 GHz DRO ×3 ×2 ×2 = 120 GHz:
Total multiplication: N = 12
PN penalty: 20·log(12) = 21.6 dB
If DRO at −120 dBc/Hz @ 10 kHz offset:
Output = −120 + 21.6 = −98.4 dBc/Hz @ 10 kHz at 120 GHz

Common Questions

Frequently Asked Questions

Why not oscillate directly at the target frequency?

Above 30 GHz, transistor gain drops, resonator Q decreases, and parasitics dominate. A multiplied 10 GHz DRO at 30 GHz has −110 dBc/Hz phase noise; a 30 GHz VCO achieves only −90 dBc/Hz. Above 100 GHz, multiplication is often the only practical approach.

What is the conversion efficiency?

Passive doublers: 6 to 10 dB loss. Passive triplers: 10 to 15 dB loss. Active doublers: 0 to 5 dB loss (or slight gain). Higher factors (×5+) cascade a doubler + tripler rather than a single ×5 stage.

Phase noise penalty?

+20·log(N) dB. Doubling: +6 dB. Tripling: +9.5 dB. Chain of ×12: +21.6 dB. Unavoidable. Start with the lowest possible source phase noise to minimize output degradation.

Related Terms

← Frequency Hopping Friis Equation →

Signal Generation

Multiplier Chain Planner

Enter target frequency and source frequency. Generate the optimal cascade of doublers and triplers with predicted output power, phase noise, and spurious levels at each stage.

Plan a Chain