CMOS PLL Design
Understanding CMOS PLL Design
A Phase-Locked Loop (PLL) is the heartbeat of any radio transceiver, acting as the frequency synthesizer that generates the precise local oscillator (LO) signals required to tune to different channels. In a monolithic System-on-Chip (SoC), the PLL must be designed entirely using the available CMOS transistors and passive components. However, traditional analog PLLs rely heavily on large loop-filter capacitors to stabilize the tuning voltage, and large capacitors consume massive amounts of expensive silicon real estate.
Furthermore, as CMOS nodes shrink (e.g., from 65nm down to 7nm), the power supply voltages drop drastically, leaving very little "voltage headroom" for analog charge pumps to operate linearly. To survive in the deep-submicron era, CMOS PLL design has undergone a radical transformation toward All-Digital Phase-Locked Loops (ADPLL). By digitizing the phase error and the loop filter, designers can shrink the PLL size exponentially, taking advantage of Moore's Law.
The All-Digital Shift (ADPLL)
In an ADPLL, the traditional analog Phase/Frequency Detector is replaced by a Time-to-Digital Converter (TDC), which measures the phase difference between the reference clock and the oscillator as a digital binary word. The massive analog loop filter capacitor is replaced by a digital infinite-impulse-response (IIR) math filter (a tiny block of logic gates). Finally, the analog VCO is replaced by a Digitally Controlled Oscillator (DCO), where frequency is tuned by switching banks of microscopic capacitors in and out of the LC tank using digital bits, rather than relying on a continuous analog varactor voltage.
Δtres = Tdelay_inverter
The quantization noise added to the PLL is governed by:
L(f) = ( (Δtres / Tvco)2 / 12 ) × (1 / fref)
As CMOS nodes shrink, the inverter delay drops below 10 picoseconds, making TDCs incredibly accurate and driving ADPLL performance past analog limits.
Comparison
| Feature | Analog Charge-Pump PLL | All-Digital PLL (ADPLL) |
|---|---|---|
| Phase Detector | Analog PFD + Charge Pump | Time-to-Digital Converter (TDC) |
| Loop Filter | Massive passive Resistors & Capacitors | Digital Accumulators & Multipliers |
| Oscillator | Analog Voltage Controlled (VCO) | Digitally Controlled (DCO) |
| Silicon Area | Large (Does not shrink well) | Tiny (Shrinks perfectly with Moore's Law) |
Frequently Asked Questions
Why do analog loop filters take up so much space on a CMOS chip?
To achieve a stable, low-noise PLL with a narrow loop bandwidth (necessary to reject reference spurs), the loop filter requires a very large capacitance (often several nanofarads). In silicon, capacitors are made by overlapping metal plates. A nanofarad capacitor can consume more physical silicon area than the entire digital microprocessor combined.
What is Fractional-N synthesis in a CMOS PLL?
A standard Integer-N PLL can only step its frequency in multiples of the reference clock (e.g., 20 MHz, 40 MHz, 60 MHz). A Fractional-N PLL uses a digital Delta-Sigma Modulator to rapidly toggle the frequency divider back and forth between two integers. The average value creates a 'fractional' division, allowing the PLL to tune in incredibly fine steps (e.g., 1 Hz resolution) while keeping a fast reference clock.
Does an ADPLL still have an analog oscillator?
Yes. Even in an 'All-Digital' PLL, the core of the Digitally Controlled Oscillator (DCO) is still a physical, analog inductor-capacitor (LC) tank resonating at the microwave frequency. The 'digital' aspect simply means the tuning capacitors are switched on and off by digital logic gates rather than a continuous analog voltage.