CMOS PA Design
Understanding CMOS Power Amplifier Design
The Holy Grail of radio engineering has always been to integrate the entire radio—from the digital CPU all the way to the antenna output—onto a single piece of cheap silicon. CMOS Power Amplifier (PA) Design is the final, and most difficult, frontier of this integration. While CMOS is brilliant for low-voltage digital logic and low-noise receivers, it is fundamentally hostile to high-power RF generation.
The core problem is voltage. As CMOS technology scales down (e.g., to 28nm or 14nm) to make digital circuits faster, the physical gate oxide layer becomes unimaginably thin—just a few atoms across. Consequently, the maximum voltage the transistor can withstand before physically rupturing drops below 1.2 Volts. To generate 1 Watt of RF power (+30 dBm) from a 1V supply, the amplifier must push massive amounts of current into a load impedance of less than 0.5 Ohms. Matching a 0.5-ohm impedance up to a 50-ohm antenna on a lossy silicon substrate creates devastating thermal and insertion losses.
Architectural Solutions
To bypass the voltage limits, CMOS PA designers use aggressive topologies. Cascode Stacking places multiple thin-oxide transistors in series so they share the large RF voltage swing, preventing any single transistor from breaking down. Transformer Combining uses on-chip primary windings to combine the output of 4 or 8 smaller push-pull amplifiers into a single secondary winding, stepping up the voltage to meet the 50-ohm antenna. RF-SOI (Silicon-on-Insulator) technology is also heavily utilized to prevent the massive RF currents from leaking into the conductive silicon substrate.
Example: Generate 1 Watt from a 1.2V CMOS supply.
Ropt = (1.2)2 / (2 × 1) = 1.44 / 2 = 0.72 Ω
The impedance matching network must transform 50Ω down to 0.72Ω. Such an extreme transformation ratio guarantees massive resistive losses in the matching inductors.
Comparison
| PA Technology | Typical VDD | Breakdown Voltage | Max Reliable Power |
|---|---|---|---|
| Deep Submicron CMOS | 1.2V | ~ 2.5V | +20 dBm (Wi-Fi, Bluetooth) |
| RF-SOI Stacked CMOS | 3.3V | ~ 10V (Stacked) | +28 dBm (Entry-level Cell) |
| GaAs InGaP HBT | 3.4V | ~ 15V | +33 dBm (Flagship Cell Phones) |
| GaN on SiC | 28V to 50V | > 150V | +50 dBm (Macro Cell Towers) |
Frequently Asked Questions
If CMOS PAs are so difficult, why do we use them?
Cost and footprint. For short-range protocols like Bluetooth, Zigbee, or IoT Wi-Fi, the required transmit power is very low (e.g., 10 milliwatts / +10 dBm). At this power level, the voltage limits of CMOS are not an issue. Integrating the PA onto the same chip as the Bluetooth microprocessor saves board space and drastically cuts the bill-of-materials cost.
Why do flagship smartphones still use GaAs for their power amplifiers?
Flagship 5G phones must transmit highly complex, high-power waveforms (up to 2 Watts) to reach distant cell towers. CMOS struggles to maintain high efficiency and strict linearity at these power levels due to the lossy substrate and low breakdown voltages. GaAs HBTs are still superior for linear mobile power, though RF-SOI is catching up for lower-tier phones.
What is an Outphasing or Polar CMOS PA?
Because CMOS acts as a terrible linear amplifier but an excellent switch, designers split complex RF signals (like OFDM) into separate phase and amplitude components in the digital domain. The phase is amplified by high-efficiency switched CMOS amplifiers, and the amplitude is restored by modulating the power supply voltage. This bypasses the need for traditional linear amplification entirely.