Bump Bond (Quantum)
Understanding Bump Bonding in Quantum RF
Superconducting quantum processors require thousands of microwave connections between the qubit chip and control/readout circuitry. Wire bonding cannot achieve the density or uniformity needed at scale. Bump bonding places an array of soft metal bumps (typically indium, which remains superconducting below 3.4 K) between two chips, then presses them together under controlled force and temperature. The result is a 3D multi-chip module with thousands of RF interconnects at 50 to 200 µm pitch, each with sub-fF parasitic capacitance.
For quantum RF at 4 to 8 GHz, the bump bond parasitics must be negligible compared to the qubit coupling capacitance (typically 1 to 10 fF). Indium bumps achieve bond resistance below 1 mΩ at millikelvin temperatures (superconducting state) and maintain mechanical integrity through hundreds of thermal cycles between room temperature and 10 mK. The bonding process must be compatible with superconducting materials (Al, Nb, TiN) without damaging the delicate Josephson junctions on the qubit chip.
Key Equations
Cbump ≈ ε0 A / d
50 µm diameter, 10 µm gap: C ≈ 0.2 fF
Indium Superconducting Tc:
Tc = 3.41 K
Bond resistance at T < Tc: 0 Ω
Thermal Contraction Mismatch:
ΔL/L = (αchip1 − αchip2) × ΔT
Si-Si: minimal | Si-sapphire: ~0.1% at 300K → 4K
Technology Comparison
| Technology | Material | Pitch | Parasitics | Cryo Compatible | Density |
|---|---|---|---|---|---|
| Indium Bump | In | 50 to 200 µm | < 0.5 fF | Yes (SC at 3.4K) | Very high |
| Wire Bond | Al, Au | ~100 µm | 0.5 to 2 fF + 0.5 nH | Yes (Al SC) | Low |
| TSV | Cu, W | 10 to 50 µm | < 0.1 fF | Limited | Highest |
| Spring Probe | BeCu | 200+ µm | 1 to 5 fF | No (non-SC) | Low |
Frequently Asked Questions
Why indium for quantum bump bonds?
Indium is superconducting below 3.4 K (zero resistance at millikelvin operating temperatures). It is soft and deformable, enabling reliable cold-welding at low bonding force. Bump resistance is literally zero in operation. Compatible with Al and Nb superconducting circuits.
How does bump bonding scale quantum processors?
Wire bonding limits qubit count because bonds must route to chip edges. Bump bonding provides area-array interconnects across the entire chip surface. A 50 µm pitch array on a 20 mm chip enables over 160,000 connections, supporting quantum processors with thousands of qubits and their control/readout lines.
What are the reliability challenges?
Thermal cycling from 300 K to 10 mK creates differential contraction stress. Indium creep and fatigue limit cycle life. Bump height uniformity must be within ±1 µm for reliable contact across the array. Bonding must not damage qubit Josephson junctions (critical current < 100 nA).