Why eliminate air bridges from MMIC designs?

Air bridges are mechanically fragile suspended metal spans that connect non-adjacent conductors over intervening traces. They are vulnerable to collapse during packaging, wire bonding, or thermal cycling, and they introduce parasitic capacitance variations from bridge height inconsistency. Bridge-free processes replace them with planar dielectric crossovers using thin-film insulator layers (SiN, SiO2, or BCB), providing mechanically robust connections with more predictable parasitics and significantly higher fabrication yield (typically 95%+ vs 80-90% with air bridges).

What are the RF performance trade-offs of bridge-free designs?

Bridge-free crossovers introduce slightly higher parasitic capacitance (0.05-0.2 pF per crossing) compared to air bridges (0.01-0.05 pF) because the dielectric layer has a higher permittivity than air. At frequencies below 40 GHz, this difference is negligible and easily absorbed into the matching network design. Above 40 GHz, careful electromagnetic simulation is required to account for the additional capacitance. The benefit is much more consistent parasitic values across a wafer, which improves design-to-measurement correlation.

What is a Bridge-Free Process? | Air-Bridge-Free MMIC

Q: How do bridge-free crossovers work in quantum circuits?

In superconducting quantum circuits, bridge-free crossovers use a deposited dielectric layer (typically 100-200 nm of SiO2 or a-Si:H) between two metal layers to create a planar crossing. The bottom conductor is patterned first, the dielectric is deposited and patterned with via openings, and the top conductor is deposited to complete the crossover. This approach is critical for qubit routing in large-scale processors where hundreds of control and readout lines must cross without electrical contact, and any air bridge collapse would short-circuit a qubit.

Definition & Purpose

A bridge-free process is a semiconductor fabrication methodology that eliminates air bridges, the fragile suspended metal spans traditionally used to connect non-adjacent conductors over intervening traces on MMICs and superconducting circuits. Instead, the process uses planar dielectric crossover structures where a thin-film insulator (SiN, SiO₂, or BCB polymer) separates two metal layers, enabling robust, mechanically stable conductor crossings with predictable parasitic characteristics.

Air bridges have been a persistent yield limiter in GaAs and InP MMIC fabrication because the suspended spans (typically 5-20 µm above the substrate) are susceptible to collapse during wafer handling, die attach, and wire bonding. In superconducting quantum computing circuits, where a single collapsed air bridge can destroy a qubit, bridge-free processes are becoming mandatory for scaling beyond 50-100 qubits. The planar crossover approach adds 2-3 mask layers to the fabrication process but eliminates the mechanical failure mode entirely.

Key Parameters

Crossover Capacitance (dielectric):

C = ε₀ × ε_r × A / t

For SiN (ε_r = 7), 10 × 10 µm overlap, 200 nm thick: C ≈ 0.03 pF

Air Bridge Capacitance: C ≈ 0.01-0.05 pF (less predictable)

Yield Improvement: 95%+ (bridge-free) vs 80-90% (air bridge)

Crossover Technology Comparison

Parameter	Air Bridge	SiN Crossover	BCB Crossover
Parasitic Capacitance	0.01-0.05 pF	0.03-0.15 pF	0.02-0.08 pF
Mechanical Strength	Fragile	Robust	Robust
Fabrication Yield	80-90%	95-99%	95-98%
Additional Mask Layers	1	2-3	2
Max Frequency	100+ GHz	60-80 GHz	80+ GHz
Cryo Compatible	Risk of collapse	Excellent	Good
Typical Use	GaAs MMIC	Quantum, GaN	InP MMIC

Practical Application

In a 100-qubit superconducting processor, control and readout lines for each qubit must cross dozens of other signal routes on the chip surface. With a traditional air bridge process, 500+ bridges per chip at 90% individual yield would produce a chip-level yield of 0.9⁵⁰⁰ ≈ 0%, making large-scale integration impossible. A bridge-free process using 200 nm SiO₂ crossovers achieves 99.5% per-crossing yield, giving chip-level yield of 0.995⁵⁰⁰ ≈ 8%, a dramatic improvement that makes multi-hundred-qubit chips manufacturable. The additional parasitic capacitance of ~0.03 pF per crossing is absorbed into the transmission line impedance design with negligible impact at the 4-8 GHz qubit operating frequencies.

Frequently Asked Questions

Why eliminate air bridges?

Air bridges are mechanically fragile, vulnerable to collapse during packaging and thermal cycling. Bridge-free planar crossovers achieve 95%+ yield versus 80-90% with bridges, and provide more predictable parasitics for design correlation.

How do bridge-free crossovers work in quantum circuits?

A dielectric layer (100-200 nm SiO₂) is deposited between two metal layers. The bottom conductor is patterned first, dielectric deposited with via openings, then the top conductor completes the crossing. Critical for scaling beyond 50+ qubits.

What are the RF trade-offs?

Slightly higher parasitic capacitance (0.03-0.15 pF vs 0.01-0.05 pF for air) due to higher dielectric permittivity. Negligible below 40 GHz; requires careful EM simulation above 40 GHz. Major benefit: much more consistent parasitics across the wafer.

Bridge-Free Process