Packaging

Bond Wire

/bond wy-er/
Die-to-package interconnect. Au/Al/Cu wire, 17.5-50μm diameter. L ≈ 1 nH/mm. @10G: 1nH = 63Ω reactance. Ribbon: 0.5-0.7 nH/mm (lower L). Parallel wires: Leff=(L−M)/2 ≈ 0.7L. Flip chip: 0.01-0.05 nH (eliminates wires). Processes: thermosonic ball (Au), ultrasonic wedge (Al), ribbon. Bond wire = frequency limit of MMIC packages.
L: ~1 nH/mm
Ribbon: 0.5-0.7
Flip chip: 0.01-0.05

Understanding Bond Wires

Bond wires are the Achilles' heel of RF packaging. No matter how brilliant the MMIC design, the die-to-package transition through bond wires determines the upper frequency limit and often degrades the performance that the die alone can achieve. At frequencies above 20 GHz, bond wire transitions require careful EM simulation and compensation network design.

The trend toward flip-chip packaging and fan-out wafer-level packaging (FOWLP) is driven by the need to eliminate bond wire inductance for 5G mmWave and automotive radar applications above 28 GHz.

Bond Wire Equations

Inductance (wire over ground):
L = (μ0/2π)(ln(4h/d)−1) nH/mm
d=25μm, h=200μm: L ≈ 0.9 nH/mm

Reactance:
XL = 2πfL
1nH @1G: 6.3Ω. @10G: 63Ω. @40G: 251Ω

Parallel wires:
Leff = (L−M)/2
M ≈ 0.3-0.5×L (100μm spacing)
2 wires: Leff ≈ 0.7×Lsingle

Interconnect Technology Comparison

TechnologyL (nH/mm)Freq LimitCostUse
Ball bond (Au)~1.0~20 GHzLowPA, LNA pkg
Wedge (Al)~1.0~20 GHzLowPower devices
Ribbon0.5-0.7~30 GHzMediummmWave mod
Flip chip0.01-0.05100+ GHzHigh5G, auto radar
FOWLP0.01-0.03100+ GHzHighSiP, SoC
Common Questions

Frequently Asked Questions

Why care?

1nH @10G = 63Ω reactance. Destroys impedance match. Ground wires: common impedance limits gain/isolation. Multiple parallel wires reduce L (2 wires ≈ 0.7L). Above 40G: bond wires impractical. Flip chip: 0.01-0.05 nH, enables 100G+. Bond wire = package frequency ceiling.

Processes?

Thermosonic ball: Au wire, spark ball, heat+ultrasonic, 10-20 bonds/sec, most common. Ultrasonic wedge: Al wire, room temp, cold weld, power devices. Ribbon: flat 25-75μm wide, lower L (0.5-0.7 nH/mm), high current. Flip chip: bumps (no wires), lowest L, best for mmWave.

Modeling?

Lumped L below 10G: L=(μ0/2π)ln(4h/d) nH/mm. Mutual M for parallel wires. Leff=(L−M)/2. Above 10G: distributed (short TL). Above 20G: full-wave EM simulation mandatory (HFSS/CST). Radiation, coupling, frequency-dependent effects. Design: compensate with matching or avoid entirely (flip chip).

RF Packaging

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