Why is gate-before-drain sequencing mandatory for GaN/GaAs?

GaN HEMTs and GaAs pHEMTs are depletion-mode devices, meaning the channel is fully conducting (ON) when the gate voltage is zero. The saturated drain current IDSS flows when VGS = 0V and VDS is applied. For a typical GaN HEMT power transistor: IDSS can be 1-10A, while the intended quiescent current IDQ for Class AB operation is only 50-500 mA (5-10% of IDSS). If the drain voltage (28-50V for GaN) is applied before the negative gate voltage (-2 to -4V), the full IDSS flows through the device, dissipating P = VDS * IDSS. For a 28V GaN HEMT with IDSS = 2A: P = 28 * 2 = 56W instantaneous dissipation, far exceeding the device thermal SOA (typically 10-15W continuous). This causes immediate junction temperature rise to destructive levels (>250C for GaN, >175C for GaAs). Even brief transients (microseconds) can cause irreversible gate oxide degradation or hot-electron trapping that permanently shifts the threshold voltage. The correct power-up sequence ensures that VGS is established at a sufficiently negative value (below the target IDQ bias) before VDS is applied, so the device never passes through the high-current, high-voltage state. A typical timing: (1) Apply VGG (negative gate supply) and wait 1-5 ms for the gate voltage to settle. (2) Verify VGS is within the target range using a comparator or ADC. (3) Enable VDD (drain supply) with a controlled ramp rate (1-10V/ms) to avoid transient current spikes from output capacitance charging (I = Cds * dVDS/dt).

What happens during power-down sequencing?

Power-down sequencing is the reverse of power-up: drain voltage must be removed before the gate voltage is released. The mandatory power-down sequence is: (1) Disable the RF input (mute or reduce drive to zero) to prevent large-signal transients during the shutdown process. This step is often overlooked but is critical for PA stages that may be operating at compression when the shutdown command arrives. (2) Ramp VDS down to zero. Controlled ramp rates (1-10V/ms) prevent inductive voltage spikes from the drain supply wiring (V = L * dI/dt). A 10 nH parasitic inductance with a 1A/us current change produces a 10V spike, which can exceed the device breakdown voltage (VDS,max) if added to the supply voltage. (3) After VDS reaches zero and drain current ceases (verified by a current sense), release VGS to zero. This allows the gate to return to VGS = 0V without consequence because VDS is already zero. If VGS is released before VDS during power-down, the same IDSS transient occurs as during incorrect power-up. This failure mode is particularly insidious because it occurs during shutdown, when monitoring circuits may already be disabled or in a low-power state. Robust sequencing designs use hardware interlocks (comparators monitoring VDS that gate the VGG enable) rather than relying solely on software/firmware timing, which can be disrupted by processor resets or firmware crashes during emergency shutdowns.

What circuits implement bias sequencing?

Bias sequencing can be implemented with dedicated ICs, discrete logic, or microcontroller-based systems. Dedicated sequencing ICs: devices like the TPS27082L, MAX16054, or LTC2928 provide programmable multi-channel enable sequencing with configurable delays (1-100 ms per channel), voltage monitoring (power-good outputs), and fault detection. The sequencing is hardwired via resistor-set timing, making it immune to firmware failures. For GaN PA applications: the gate supply is typically channel 1 (enables first, disables last) and the drain supply is channel 2 (enables second, disables first). Some ICs include integrated charge pumps for generating the negative gate voltage from a positive supply. Discrete RC delay circuits: the simplest approach uses an RC time constant to delay the drain supply enable signal relative to the gate supply. A comparator monitors the gate voltage; when VGS reaches the target value, it triggers a one-shot or Schmitt trigger that enables the drain supply FET switch after a fixed delay (set by RC). Advantages: zero firmware dependency, very low cost. Disadvantages: timing varies with component tolerances (typically +/-20%), no intelligent fault response. Microcontroller-based: an ADC monitors VGS and VDS, and firmware controls enable FETs in the correct sequence with programmable delays and slew rates. Advantages: flexible timing, logging, fault diagnosis, remote control. Disadvantages: firmware bugs can cause incorrect sequencing; must include hardware backup interlocks (watchdog timers, comparator-based hard shutdowns) to protect against processor failures. For military and aerospace applications (MIL-STD-1275), radiation-hardened sequencing ICs or triple-redundant comparator circuits are required to ensure sequencing integrity in radiation environments.

Power Amplifier / Protection

Bias Sequencing

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Controlled power-up/power-down ordering for RF transistors to prevent destructive overcurrent. Depletion-mode GaN/GaAs: gate voltage (V_GS negative) must be applied before drain voltage (V_DS). Without sequencing, I_D spikes to I_DSS (10–100× I_DQ), exceeding SOA. Power-down reverses: V_DS off first, then V_GS. Timing: 1–10 ms delays, enforced by sequencing ICs or hardware interlocks.

Order: V_GS → V_DS

Delay: 1–10 ms

Risk: I_DSS transient

Understanding Bias Sequencing

GaN HEMTs and GaAs pHEMTs are depletion-mode devices: the channel conducts at V_GS = 0 V, drawing the full saturated current I_DSS. If the drain supply (28–50 V) is applied before the negative gate bias pinches off the channel, instantaneous dissipation can reach P = V_DS × I_DSS (tens of watts), destroying the device within microseconds. Bias sequencing ensures the gate is always in control before high voltage appears at the drain.

Power-down is equally critical. If the gate voltage is released while V_DS is still present, the same I_DSS transient occurs. Robust designs use hardware interlocks (comparators gating V_DD enable based on V_GS state) rather than firmware-only sequencing, which can fail during unexpected resets or crashes.

Sequencing Timing

Power-Up Sequence:
1. Apply V_GG (negative gate supply)
2. Wait 1–5 ms, verify V_GS < V_p
3. Enable V_DD, ramp 1–10 V/ms
4. I_charge = C_ds × dV_DS/dt (transient)

Power-Down Sequence:
1. Mute RF input
2. Ramp V_DS → 0 (1–10 V/ms)
3. Verify I_D = 0 via sense resistor
4. Release V_GS → 0

Transient Risk:
P_transient = V_DS × I_DSS
28 V × 2 A = 56 W (SOA < 15 W)

Sequencing Implementation

Method	Reliability	Flexibility	Cost	Best For
Dedicated IC	High (hardwired)	Low (fixed timing)	Moderate	Production PA modules
Discrete RC + comparator	High (no firmware)	Low	Low	Simple designs
MCU + ADC	Medium (firmware risk)	High (programmable)	Moderate	Lab prototypes, SDR
MCU + hardware interlock	High (dual protection)	High	Higher	Mil/aero, base station

Device Technology Requirements

Device	Mode	Sequence	V_GS Range	Risk
GaN HEMT	Depletion	V_GS → V_DS	−2 to −4 V	I_DSS = 1–10 A
GaAs pHEMT	Depletion	V_GS → V_DS	−0.5 to −2 V	Gate burnout
LDMOS	Enhancement	V_DS first OK	0 to +3 V	Low (normally off)
SiGe HBT	Enhancement	V_CE first OK	V_BE = 0.7–0.9 V	Thermal runaway

Common Questions

Frequently Asked Questions

Why gate before drain?

GaN/GaAs are depletion-mode: channel ON at V_GS = 0. Without gate bias, I_DSS flows (1–10 A) at full V_DS (28–50 V). P = 56 W transient exceeds 15 W SOA. Apply V_GS negative first, verify channel pinched off, then enable V_DS. 1–5 ms delay typical.

Power-down sequence?

Reverse: mute RF, ramp V_DS to 0 (1–10 V/ms to avoid inductive spikes), verify I_D = 0, then release V_GS. Releasing V_GS first causes same I_DSS transient. Hardware interlocks (V_DS comparator gating V_GG release) protect against firmware crashes.

Implementation options?

Dedicated IC (hardwired, most reliable). Discrete RC + comparator (simple, no firmware). MCU + ADC (flexible but firmware-vulnerable). Best practice: MCU for monitoring/logging + hardware interlock for fail-safe protection. LDMOS/SiGe enhancement-mode: normally off, no sequencing needed.

Related Terms

← Bias Point Optical Bias Stability →

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