How do the inductor and capacitor values determine bias tee bandwidth?

The bias tee bandwidth is bounded by two critical frequencies: Low-frequency cutoff (f_low): set by the DC-blocking capacitor. The capacitor must present low impedance relative to 50Ω at the lowest RF frequency. X_C = 1/(2πf_low·C) ≤ 5Ω (10% of Z₀). For f_low = 10 MHz: C ≥ 1/(2π·10⁷·5) = 3.2 nF. Standard choice: 10-100 nF ceramic + 1-10 μF tantalum in parallel. For f_low = 100 kHz: C ≥ 318 nF. This is why low-frequency bias tees use large electrolytic or tantalum capacitors. High-frequency limit (f_high): set by the RF choke inductor's self-resonant frequency (SRF). Above the SRF, the inductor's parasitic capacitance C_parasitic dominates, and the choke becomes a capacitor, allowing RF to leak into the DC port. SRF = 1/(2π·√(L·C_parasitic)). For adequate RF blocking: f_high ≈ 0.5 × SRF (impedance drops rapidly above SRF). For a 100 nH inductor with 0.1 pF parasitic: SRF = 1/(2π·√(100×10⁻⁹·0.1×10⁻¹²)) = 50.3 GHz. Usable to ~25 GHz. Design trade-off: larger L provides better low-frequency RF blocking (X_L = 2πf·L >> 50Ω requires L >> 50/(2πf)). At 10 MHz: L >> 796 nH. But larger L has lower SRF due to more winding capacitance. Solution: multi-section choke with ferrite bead (low-freq) + air-core inductor (high-freq) + thin-film spiral (mmWave). This extends the effective choke bandwidth from DC to >50 GHz.

What causes insertion loss and distortion in bias tees?

Bias tee insertion loss has several frequency-dependent contributions: 1) Capacitor ESR: the DC-blocking capacitor has equivalent series resistance (ESR) that dissipates RF power. Ceramic capacitors: ESR = 0.01-0.1Ω (negligible at RF). Tantalum/electrolytic (used for low f_low): ESR = 0.1-5Ω. IL contribution: 20·log₁₀(1 + ESR/2Z₀). At ESR = 1Ω: IL = 0.087 dB. 2) Inductor resistive loss: DC resistance of the choke winding and skin-effect losses at RF. A 100 nH coil with 1Ω resistance causes minimal IL through the RF path directly, but any RF current flowing through the choke (due to imperfect blocking) is dissipated. 3) Impedance mismatch: the capacitor and inductor junction create a reactive discontinuity. The parallel combination of Z_L (choke) and Z_C (cap + load) deviates from 50Ω, creating VSWR. At mid-band: Z_junction ≈ 50Ω (by design). Near f_low: capacitor impedance rises, Z_junction increases, VSWR degrades. Near inductor SRF: choke impedance drops, RF leaks into DC port. 4) Distortion: for high-power applications, the inductor core material (ferrite) introduces nonlinearity. Ferrite permeability is field-dependent, creating harmonics and IMD. For sensitive measurements (IP3 > +40 dBm): use air-core inductors only. Ferrite bias tees typically limit IP3 to +30-40 dBm. 5) Video leakage: in pulsed RF applications, the modulation envelope (video bandwidth) must pass through the bias tee. If f_low is too high, the pulse shape is distorted. Rule: f_low ≤ 1/(10·τ_pulse) for <5% pulse droop.

How are bias tees used in test and measurement?

Bias tees are fundamental to semiconductor characterization and active device testing: 1) LNA noise figure measurement: the DUT (LNA) requires DC bias (typically 3-5 V, 50-200 mA). A bias tee at the DUT input allows the noise source and DUT to share a single coaxial connection, while DC power is injected through the DC port. A second bias tee at the output separates the amplified RF from the drain supply. Critical: the bias tee insertion loss adds directly to the measured noise figure. A 0.5 dB bias tee IL means 0.5 dB measurement error in NF. 2) Power amplifier load-pull: bias tees supply gate and drain voltages while presenting calibrated RF source and load impedances. High-current bias tees (2-10 A) are needed for GaN PA characterization at 28-48 V drain voltage. Power handling: 10-50 W through the RF path. 3) Photodiode testing: reverse-bias voltage (5-30 V) is supplied through the bias tee while the detected RF photocurrent flows to the spectrum analyzer or oscilloscope. The bias tee bandwidth must exceed the photodiode bandwidth (typically 10-40 GHz). 4) On-wafer probing: integrated bias tees in GSG (ground-signal-ground) probe assemblies supply DC to the DUT pads while the VNA measures S-parameters. Probe station bias tees operate DC to 67+ GHz. 5) Antenna feed: remote-mounted active antennas and tower-mounted amplifiers receive DC power through the coaxial feedline via bias tee injection at the base station.

Passive Components

Bias Tee

Q: How are bias tees used in test and measurement?

Bias tees are fundamental to semiconductor characterization and active device testing: 1) LNA noise figure measurement: the DUT (LNA) requires DC bias (typically 3-5 V, 50-200 mA). A bias tee at the DUT input allows the noise source and DUT to share a single coaxial connection, while DC power is injected through the DC port. A second bias tee at the output separates the amplified RF from the drain supply. Critical: the bias tee insertion loss adds directly to the measured noise figure. A 0.5 dB bias tee IL means 0.5 dB measurement error in NF. 2) Power amplifier load-pull: bias tees supply gate and drain voltages while presenting calibrated RF source and load impedances. High-current bias tees (2-10 A) are needed for GaN PA characterization at 28-48 V drain voltage. Power handling: 10-50 W through the RF path. 3) Photodiode testing: reverse-bias voltage (5-30 V) is supplied through the bias tee while the detected RF photocurrent flows to the spectrum analyzer or oscilloscope. The bias tee bandwidth must exceed the photodiode bandwidth (typically 10-40 GHz). 4) On-wafer probing: integrated bias tees in GSG (ground-signal-ground) probe assemblies supply DC to the DUT pads while the VNA measures S-parameters. Probe station bias tees operate DC to 67+ GHz. 5) Antenna feed: remote-mounted active antennas and tower-mounted amplifiers receive DC power through the coaxial feedline via bias tee injection at the base station.

/BY-us TEE/

Three-port frequency-diplexing network combining DC bias and RF signals. DC-blocking capacitor (X_C << 50Ω) passes RF, blocks DC. RF choke inductor (X_L >> 50Ω) passes DC, blocks RF. Bandwidth: 100 kHz to 110 GHz. IL: 0.3 to 1.5 dB. Max current: 0.5 to 10 A. Upper limit set by choke SRF = 1/(2π√(LC_p)). Used for LNA biasing, photodiode supply, and active antenna feeds.

BW: 100 kHz–110 GHz

IL: 0.3–1.5 dB

I_max: 0.5–10 A

Understanding Bias Tees

Many RF systems require DC power to be delivered to a remote active device through the same coaxial cable that carries the RF signal. Low-noise amplifiers mounted at the antenna feed, photodiodes in fiber-optic receivers, and active antenna elements all need DC bias that must be injected without disturbing the RF signal path. The bias tee solves this with an elegantly simple topology: an inductor-capacitor diplexer that routes DC and RF to their respective ports.

The design challenge lies in achieving wide bandwidth. The DC-blocking capacitor must be large enough for low-frequency operation (X_C < 5Ω at f_low), while the RF choke must maintain high impedance across the entire RF band. Above the choke's self-resonant frequency, parasitic winding capacitance creates a low-impedance path that leaks RF into the DC supply. Multi-section choke designs, combining ferrite beads with air-core spirals, extend usable bandwidth into the millimeter-wave range.

Bandwidth & Component Sizing

Low-Frequency Cutoff (DC-block cap):
X_C = 1/(2πf·C) ≤ 5Ω
f_low = 10 MHz ⇒ C ≥ 3.2 nF
f_low = 100 kHz ⇒ C ≥ 318 nF

Choke Self-Resonant Frequency:
SRF = 1/(2π√(L·C_p))
L = 100 nH, C_p = 0.1 pF: SRF = 50.3 GHz
Usable f_high ≈ 0.5 × SRF ≈ 25 GHz

Choke Impedance Requirement:
X_L = 2πf·L >> 50Ω
At 10 MHz: L >> 796 nH

Bias Tee Specifications by Application

Application	Freq Range	I_DC	V_DC	IL (dB)	Key Req.
LNA bias	1–40 GHz	50–200 mA	3–8 V	<0.5	Low NF impact
PA characterization	0.5–18 GHz	2–10 A	28–50 V	<1.0	High power/current
Photodiode	DC–40 GHz	1–20 mA	5–30 V	<0.5	Wideband, low noise
Tower-mount amp	0.7–6 GHz	0.5–3 A	12–48 V	<0.3	Lightning protection
On-wafer probe	DC–67 GHz	100 mA	30 V	<1.0	Integrated in GSG

Common Questions

Frequently Asked Questions

How do L and C set bandwidth?

f_low: C must give X_C < 5Ω (C ≥ 3.2 nF at 10 MHz). f_high: choke SRF = 1/(2π√LC_p), usable to 0.5×SRF. Multi-section chokes (ferrite + air-core + thin-film) extend to >50 GHz.

Loss and distortion?

Cap ESR adds 0.01 to 0.1 dB. Impedance mismatch at band edges degrades VSWR. Ferrite cores limit IP3 to +30 to 40 dBm (use air-core for >+40 dBm). Pulse droop: f_low ≤ 1/(10·τ).

Test & measurement uses?

NF measurement (IL adds directly to NF error). PA load-pull (2 to 10 A, 28 to 48 V). Photodiode reverse bias (DC to 40 GHz). On-wafer GSG probing (DC to 67 GHz). Antenna feed DC injection.

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