What determines RF switch insertion loss?

Insertion loss in an RF switch comes from the on-state resistance (Ron) of the switching element (FET channel or PIN diode I-layer) and any parasitic losses in the package, interconnects, and matching network. For a FET switch: IL approximately equals 20*log10(1 + Ron/(2*Z_0)) dB, where Z_0 is 50 ohms. A FET with Ron = 1 ohm gives IL = 0.09 dB; Ron = 5 ohms gives IL = 0.43 dB. For PIN diodes, the on-resistance is controlled by forward bias current: lower resistance at higher current, but more DC power consumption. Series-shunt switch topologies improve isolation at the cost of slightly higher insertion loss (additional shunt FET parasitic capacitance). Multi-stack FET designs (series FETs on the same substrate) handle higher voltage swings but increase Ron proportionally, raising insertion loss. The figure of merit for switch FETs is Ron times Coff (in femtoseconds), which fundamentally limits the IL-isolation trade-off.

How is switch isolation achieved?

Isolation measures how well the switch attenuates signals through the off path. For a simple series FET switch, isolation is determined by the off-state capacitance (Coff): ISO approximately equals 20*log10(2*pi*f*Coff*Z_0/2) dB. A FET with Coff = 50 fF at 2 GHz gives approximately 20 dB isolation. Lower Coff requires smaller FET width, but this increases Ron, creating a fundamental trade-off characterized by the Ron times Coff figure of merit. Series-shunt topology improves isolation by adding a shunt FET to ground on the off path: when the series FET is off (high impedance), the shunt FET is on (low impedance to ground), providing an additional 10 to 20 dB isolation. This is the standard topology for antenna switches in cellular handsets. Absorptive switches add a termination resistor on the off port to maintain 50 ohm match regardless of switch state, important for test equipment and systems sensitive to reflection.

Which switch technology should I use?

PIN diode: best for high power (watts to kilowatts) because forward-biased I-layer handles high RF voltage linearly. Insertion loss 0.3 to 1 dB, isolation 40 to 60 dB. Switching speed limited by carrier lifetime: 50 to 500 nanoseconds. Requires DC bias current (10 to 100 mA). Used in radar T/R modules and base station switches. GaAs pHEMT: fast switching (1 to 10 ns), moderate power (100 mW to 1 W), broadband (DC to 40 GHz). IL 0.3 to 1 dB. Used in instrumentation, military, and high-frequency switching. SOI CMOS: lowest cost, highly integrated (SP16T in single die for antenna switch modules), moderate performance. IL 0.5 to 1.5 dB, ISO 20 to 35 dB. FOM 150 to 200 fs. Dominates smartphone RF front ends (billions of units). MEMS: lowest insertion loss (0.1 to 0.3 dB) and highest isolation (40 to 60 dB), but slow switching speed (1 to 100 microseconds) and limited reliability. Used in test equipment and satellite switchboards.

RF Switching

SPDT Switch

/ess-pee-dee-tee/ — Single-Pole Double-Throw

Routes common port to one of two outputs. IL 0.2-1.5 dB, isolation 20-50 dB, speed 1 ns-10 μs. Technologies: PIN (high power, kW), GaAs pHEMT (fast, DC-40 GHz), SOI CMOS (low cost, SP16T integrated, smartphone ASMs), MEMS (lowest loss, slow). FOM = R_on×C_off (fs): limits IL-isolation trade-off. Series-shunt topology: +10-20 dB isolation. Used for TDD T/R, antenna diversity, band selection.

IL: 0.2-1.5 dB

ISO: 20-50 dB

FOM: R_on×C_off

Understanding SPDT Switches

The RF switch is the traffic controller of the wireless front end. Every time a TDD radio transitions between transmit and receive, an SPDT switch routes the antenna from the PA output to the LNA input (or vice versa). Every time a multi-band phone changes operating frequency, an SPnT switch selects the appropriate filter path. A modern 5G smartphone uses 10+ RF switches handling dozens of frequency bands, carrier aggregation combinations, and antenna diversity paths.

The fundamental trade-off in switch design is between insertion loss (determined by the on-state resistance R_on) and isolation (determined by the off-state capacitance C_off). The product R_on×C_off is a technology-dependent figure of merit that cannot be improved by circuit design alone: it requires a better transistor or switch technology. SOI CMOS achieves 150-200 fs, GaAs achieves 100-150 fs, and MEMS achieves near-zero (mechanical contact).

Switch Performance Equations

Insertion loss (series FET):
IL ≈ 20 log(1+R_on/(2Z₀)) dB
R_on=1Ω: IL=0.09 dB
R_on=5Ω: IL=0.43 dB

Isolation (series FET):
ISO ≈ 20 log(1/(2πfC_offZ₀)) dB
C_off=50 fF, 2 GHz: ISO≈20 dB

Figure of merit:
FOM = R_on×C_off (fs)
SOI CMOS: 150-200 fs
GaAs: 100-150 fs
PIN: N/A (different mechanism)

Power handling:
P_max = V_pk²/(2Z₀)
N stacked FETs: V_max = N×V_break

RF Switch Technology Comparison

Technology	IL	Isolation	Speed	Power	Application
SOI CMOS	0.5-1.5 dB	20-35 dB	50-200 ns	1-2 W	Smartphone ASM
GaAs pHEMT	0.3-1 dB	25-45 dB	1-10 ns	0.1-1 W	Test, military
PIN diode	0.3-1 dB	40-60 dB	50-500 ns	1-1000 W	Radar T/R
MEMS	0.1-0.3 dB	40-60 dB	1-100 μs	0.5-2 W	Satellite, test
Electromech.	0.03-0.1 dB	60-90 dB	5-20 ms	100+ W	Test routing

Common Questions

Frequently Asked Questions

What determines switch IL?

On-state resistance (R_on): IL ≈ 20log(1+R_on/100) dB. R_on=1Ω: 0.09 dB. R_on=5Ω: 0.43 dB. FET switches: R_on = f(gate width, V_GS). Wider FET = lower R_on but higher C_off. PIN: R_on controlled by bias current. Series-shunt adds shunt FET parasitics. Multi-stack FETs: R_on ∝ N stacks (higher power but more loss).

How is isolation achieved?

Series FET: C_off determines isolation. ISO ≈ 20log(1/ωC_off Z_0). 50 fF at 2 GHz: ~20 dB. Series-shunt: shunt FET grounds off-path, adds 10-20 dB. FOM = R_on×C_off limits trade-off. SOI: 150-200 fs. GaAs: 100-150 fs. Absorptive: termination R on off-port maintains 50Ω match regardless of state.

Which technology?

PIN: high power (kW), 40-60 dB ISO, needs DC bias, radar T/R. GaAs pHEMT: fastest (1-10 ns), DC-40 GHz, test/military. SOI CMOS: cheapest, SP16T integrated, billions of smartphones. MEMS: lowest loss (0.1 dB), highest ISO, slow (1-100 μs), satellite/test. Choice depends on power/speed/cost/integration requirements.

Related Terms

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