Noise Mechanisms

Flicker Noise (1/f Noise)

/flik-er noyz/ (1/f)
Flicker noise has PSD proportional to 1/f. In oscillators, it upconverts to close-in phase noise with 1/f3 slope (Leeson model). The 1/f corner varies dramatically: SiGe HBT 1-10 kHz (best), Si CMOS 10-100 kHz, GaAs pHEMT 100 kHz-1 MHz, GaN HEMT 1-10 MHz (worst). Caused by carrier trapping at defects. Lower corner = better close-in phase noise.
PSD: S(f) = K/f
SiGe: 1-10 kHz corner
GaN: 1-10 MHz corner

Understanding Flicker Noise

Flicker noise is the hidden enemy of close-in phase noise. While thermal noise is flat and predictable, flicker noise rises as you approach DC, and when it enters an oscillator's nonlinear active device, it upconverts around the carrier as amplitude and phase modulation. The result: the close-in phase noise of an oscillator is often dominated by the active device's flicker noise, not thermal noise. Choosing the right transistor technology is therefore critical for VCO design.

Leeson Phase Noise Model

Flicker noise PSD:
S(f) = KfIa/(fbCoxWL)
a ≈ 2, b ≈ 1

Corner frequency:
fc = where S1/f = Swhite

Hooge parameter:
SV/V² = αH/(f·N)

1/f Corner by Technology

Technology1/f CornerClose-in PNMechanismBest For
SiGe HBT1-10 kHzExcellentBulk transportVCOs, PLLs
Si CMOS10-100 kHzGoodInterface trapsIntegrated VCOs
InP HBT10-100 kHzGoodBuffer defectsmmWave VCOs
GaAs pHEMT100 kHz-1 MHzModerateSurface statesLNAs, mixers
GaN HEMT1-10 MHzPoorThreading dislocationsPower amps only

Key Equations

Decibel conversion:
Power: dB = 10log(P2/P1)
Voltage: dB = 20log(V2/V1)

dBm to watts:
P(W) = 10(dBm−30)/10
0 dBm = 1 mW, +30 dBm = 1 W

Wavelength:
λ = c/f = 300/f(MHz) meters

Comparison

TechnologyfcMechanismPN impactApplication
SiGe HBT1–5 kHzBase recombBestVCO/LO
Si BJT5–50 kHzSurface trapsGoodPrecision osc
GaAs pHEMT10–100 MHzDX centersPoorLNA only
Si CMOS0.5–10 MHzOxide trapsModerateDigital PLL
GaN HEMT1–50 MHzBuffer trapsModeratePA bias
Common Questions

Frequently Asked Questions

Phase noise impact?

Flicker noise upconverts in oscillators to 1/f^3 close-in phase noise. Leeson model: three regions (1/f^3, 1/f^2, flat). Lower 1/f corner = narrower 1/f^3 region = better close-in PN. SiGe HBT is best technology choice.

Technology differences?

SiGe HBT: 1-10 kHz (bulk transport, no surface). Si CMOS: 10-100 kHz (interface traps). GaN HEMT: 1-10 MHz (epitaxial defects). Use SiGe for VCOs; GaN only for power.

Reduction techniques?

High-Q resonator filters close-in noise. Large-signal operation reduces upconversion. Source degeneration. PLL loop BW above 1/f corner suppresses VCO flicker. Technology selection is most impactful.

Low-Noise Design

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