How does clock jitter affect ADC performance?

Clock jitter introduces timing uncertainty in the ADC sampling instant. The resulting voltage error is proportional to the signal slew rate times the jitter: V_error = 2*pi*f_signal*A*t_jitter. The maximum achievable SNR due to jitter alone is SNR_jitter = minus 20*log10(2*pi*f_signal*t_jitter_rms). For a 100 MHz signal with 100 femtosecond RMS jitter: SNR = minus 20*log(2*pi*100e6*100e-15) = 64 dB, limiting the effective number of bits to about 10.3. For a 14-bit ADC sampling a 1 GHz signal, the clock jitter must be below 25 femtoseconds RMS. This is why high-speed ADC systems require extremely low-jitter clock sources, typically ultra-low-phase-noise crystal oscillators followed by jitter-cleaning PLLs.

What types of reference oscillators are used?

XO (crystal oscillator): basic quartz crystal, stability 20 to 50 ppm, lowest cost. TCXO (temperature-compensated): analog or digital compensation, 0.5 to 2 ppm stability over minus 40 to plus 85 C, used in cellular handsets and GPS. VCXO (voltage-controlled): tunable by varactor, used in PLLs for frequency pulling. OCXO (oven-controlled): crystal maintained at constant temperature, 0.01 to 0.1 ppb stability, used in base stations, test equipment, and radar. Atomic references: rubidium (Rb) at 10 to the minus 11, cesium (Cs) at 10 to the minus 13, hydrogen maser at 10 to the minus 15. GPS-disciplined oscillators (GPSDO) lock a local OCXO to GPS timing for long-term accuracy of 10 to the minus 12.

What is the relationship between phase noise and jitter?

Phase noise and jitter are two representations of the same phenomenon: timing instability. Phase noise is measured in the frequency domain as the spectral density of phase fluctuations (dBc/Hz at offset frequencies). Jitter is measured in the time domain as RMS timing deviation (seconds). They are related by integration: t_jitter_rms = (1/(2*pi*f_carrier)) times sqrt(2 times integral of 10 to the power of (L(f)/10) df), where L(f) is the single-sideband phase noise in dBc/Hz and the integral is over the offset frequency range of interest. A 100 MHz oscillator with phase noise of minus 150 dBc/Hz at 10 kHz offset has approximately 30 femtoseconds RMS jitter when integrated from 10 Hz to 10 MHz. For ADC clocking, the integration bandwidth should match the Nyquist bandwidth of the ADC.

Timing Reference

RF Clock

/klok/

Timing reference synchronizing frequency generation, data conversion, and digital processing. Crystal oscillators (10-52 MHz) provide stable reference; PLLs multiply to operating frequency. Clock jitter degrades ADC SNR: SNR = −20log(2πf×t_jitter). TCXO: 0.5-2 ppm, cellular/GPS. OCXO: 0.01-0.1 ppb, base stations/radar. Atomic (Rb/Cs): 10⁻¹¹ to 10⁻¹³. GPSDO: long-term 10⁻¹² accuracy.

TCXO: 0.5-2 ppm

OCXO: 0.01-0.1 ppb

Jitter: 25-500 fs

Understanding RF Clocks

Every RF system begins with a clock. The reference oscillator is the heartbeat of the entire signal chain, providing the stable timing reference from which all other frequencies are derived. A base station's local oscillator frequencies, sampling clocks, and digital processing timers all trace back to a single reference. If that reference drifts by 1 ppm, every derived frequency shifts by the same 1 ppm, potentially causing call drops, data errors, or loss of synchronization.

The quality of the clock manifests in two dimensions: accuracy (how close to the nominal frequency) and stability (how much it varies over time and temperature). Short-term stability determines phase noise and jitter, which limit ADC dynamic range and synthesizer spectral purity. Long-term stability determines frequency drift, which affects channel spacing and carrier frequency accuracy requirements.

Clock Performance Equations

ADC jitter-limited SNR:
SNR = −20 log(2πf_sig×t_j,rms)
100 MHz, 100 fs: SNR = 64 dB
1 GHz, 25 fs: SNR = 62 dB
ENOB = (SNR−1.76)/6.02

Jitter from phase noise:
t_j = (1/2πf_c)√(2∫10^L(f)/10df)
Integrate over offset BW of interest

Frequency accuracy:
Δf = f₀ × stability (ppm)
2.4 GHz, 1 ppm: Δf = 2.4 kHz
5G NR requires <0.1 ppm at gNB

Reference Oscillator Comparison

Type	Stability	Phase Noise	Size	Power	Application
XO	20-50 ppm	−130 dBc/Hz	2×2 mm	1-5 mW	Consumer IoT
TCXO	0.5-2 ppm	−140 dBc/Hz	3×3 mm	3-10 mW	Cellular, GPS
OCXO	0.01-0.1 ppb	−160 dBc/Hz	25×25 mm	1-3 W	BTS, test, radar
Rubidium	10⁻¹¹	−150 dBc/Hz	50×50 mm	5-15 W	Telecom, military
GPSDO	10⁻¹²	−155 dBc/Hz	Variable	3-10 W	BTS, timing

Common Questions

Frequently Asked Questions

Clock jitter impact on ADC?

Timing uncertainty causes voltage error: V_err = 2πf×A×t_jitter. SNR_jitter = −20log(2πf×t_j). 100 MHz at 100 fs: 64 dB (10.3 ENOB). 1 GHz at 25 fs: 62 dB. 14-bit ADC sampling 1 GHz needs <25 fs. Ultra-low-phase-noise OCXO + jitter-cleaning PLL required for wideband direct sampling.

Oscillator types?

XO: basic quartz, 20-50 ppm, cheapest. TCXO: temp-compensated, 0.5-2 ppm, cellular/GPS. OCXO: oven-stabilized, 0.01-0.1 ppb, BTS/radar. Atomic: Rb (10−11), Cs (10−13), maser (10−15). GPSDO: OCXO locked to GPS timing, 10−12 long-term. Cost/power/size scale with stability.

Phase noise vs. jitter?

Same phenomenon: timing instability. Phase noise: frequency domain (dBc/Hz at offsets). Jitter: time domain (seconds RMS). t_j = (1/2πf)√(2∫10^(L(f)/10)df). 100 MHz, −150 dBc/Hz @ 10 kHz: ~30 fs (integrated 10 Hz to 10 MHz). For ADC clocking, integration BW should match Nyquist bandwidth.

Related Terms

← Circulator CMOS →

Timing Systems

Request a Quote

Need clock design, jitter optimization, or timing synchronization? Contact our team.

Get in Touch