How do voltage clearance requirements differ from RF clearance?

Voltage clearance rules prevent electrical breakdown (arcing) between conductors at different potentials. IPC-2221B specifies minimum spacing based on voltage difference, conductor configuration (internal vs external layers), and altitude. For sea-level external conductors: 0.1 mm per volt up to 15V, then approximately 0.25 mm per 100V above 15V for uncoated boards. Conformal coating roughly doubles the voltage withstand per unit spacing. These are separate from and additional to RF clearance requirements. In mixed RF/power designs, the controlling clearance is whichever is larger. For example, a bias feed network carrying 28V to a GaN power amplifier needs both voltage clearance (IPC minimum for 28V) and RF clearance (decoupled via inductors/capacitors) to prevent RF energy from coupling into the DC supply.

How are clearance rules implemented in PCB design software?

Modern EDA tools (Altium Designer, Cadence Allegro, KiCad, Mentor Xpedition) implement clearance rules through Design Rule Checks (DRC). Rules are defined as class-to-class constraints: net class 'RF_50ohm' to net class 'Digital' might require 40 mil clearance, while 'RF_50ohm' to 'RF_50ohm' requires 50 mil. Advanced tools support conditional rules (clearance varies by layer, region, or component), differential pair clearance (maintaining consistent gap for impedance), and keepout zones around sensitive RF components. DRC runs in real-time during routing or as a batch check before fabrication. For RF designs, supplement DRC with electromagnetic simulation (Ansys HFSS, Keysight ADS Momentum) to verify that the clearances achieve the required isolation at operating frequency, since DRC only checks geometry, not electromagnetic coupling.

PCB Design & Layout

Clearance Rule

Q: What clearance is needed between RF traces?

For microstrip and stripline RF traces on standard PCB substrates (FR-4, Rogers), the minimum clearance to maintain impedance control and minimize coupling is 3 to 5 times the substrate height (trace-to-ground distance). For a typical 10 mil substrate height, this means 30 to 50 mil (0.75 to 1.25 mm) clearance between parallel RF traces. This provides greater than 40 dB isolation for parallel runs under 10 mm. For longer parallel runs or higher isolation requirements (filter sections, LNA to PA isolation), use ground-filled gaps with via fences (via spacing less than lambda/10) between traces to achieve 60 to 80 dB isolation. Trace-to-board-edge clearance should be at least 3 times substrate height to maintain impedance accuracy.

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A PCB design constraint specifying minimum spacing between conductive features (traces, pads, vias, copper pours) to prevent arcing, crosstalk, and impedance perturbation. In RF PCB design, clearance rules are more stringent than digital: microwave traces require 3 to 5 times substrate height between RF traces and other conductors to maintain impedance control and achieve >40 dB isolation. Implemented through Design Rule Checks (DRC) in EDA tools with net-class-to-net-class constraints, supplemented by EM simulation for verification.

Category: PCB Design & Layout

RF Spacing: 3 to 5× substrate height

Standard: IPC-2221B (voltage)

Understanding Clearance Rules

Clearance rules serve three distinct purposes in PCB design. First, voltage withstand: conductors at different potentials must be separated by enough distance to prevent dielectric breakdown of the PCB substrate and surrounding air. IPC-2221B defines minimum spacings based on voltage, layer configuration, and altitude. Second, crosstalk and coupling: adjacent traces exchange energy through mutual capacitance and inductance, and the coupling coefficient increases as spacing decreases. For digital circuits, a 3W rule (spacing equals 3 times trace width) provides adequate isolation. For RF circuits, the requirement is much stricter because even -40 dB coupling can degrade receiver sensitivity or cause oscillation in amplifier circuits.

Third, impedance control: the characteristic impedance of a microstrip or stripline trace depends not only on its width and substrate height but also on proximity to adjacent conductors. A 50 Ω trace passing near a parallel ground pour can see its impedance shift by 5 to 10 Ω if the pour edge is too close, creating a discontinuity that reflects RF energy and degrades return loss. The general rule for microstrip is to keep adjacent conductors at least 3 times the substrate height away from the RF trace edges. For maximum isolation between parallel RF traces (filter sections, LNA-PA separation), ground-filled gaps with via fences at λ/10 spacing provide 60 to 80 dB isolation. Modern EDA tools implement these as class-to-class rules in the DRC engine, but EM simulation is essential to verify that geometric clearances translate to adequate electromagnetic isolation at the operating frequency.

RF Clearance Calculations

Minimum RF Trace Clearance:
S ≥ 3 × h (basic) ; S ≥ 5 × h (high isolation)

Coupling Coefficient (parallel microstrip):
k ≈ (S/h)^-2 for S/h > 2

Via Fence Spacing:
p ≤ λ/10 at highest operating frequency

Where S = trace-to-trace spacing, h = substrate height (trace to ground), p = via pitch, λ = wavelength in substrate. Example: h = 10 mil, S = 30 mil gives k ≈ -20 dB for short parallel runs.

Common RF PCB Clearance Rules

Rule	Typical Value	Purpose	Standard
RF trace-to-trace	30 to 50 mil	Impedance control, isolation	RF design practice
RF trace-to-ground pour	≥3× substrate height	Impedance accuracy	RF design practice
Voltage clearance	0.1 mm/V to 15V	Breakdown prevention	IPC-2221B
Digital 3W rule	3× trace width	Crosstalk <-40 dB	General practice
Via fence pitch	≤λ/10	Ground isolation wall	RF design practice

Common Questions

Frequently Asked Questions

What clearance is needed between RF traces?

Minimum 3 to 5 times substrate height (30 to 50 mil for 10 mil substrate) for >40 dB isolation. For higher isolation, use ground-filled gaps with via fences (λ/10 pitch) for 60 to 80 dB. Trace-to-board-edge: at least 3× substrate height for impedance accuracy.

How do voltage clearance requirements differ from RF?

Voltage clearance prevents arcing (IPC-2221B: ~0.1 mm/V to 15V). RF clearance prevents coupling and impedance perturbation. In mixed RF/power designs, use whichever is larger. Conformal coating doubles voltage withstand per unit spacing.

How are clearance rules implemented in EDA tools?

DRC with class-to-class constraints (e.g., RF_50ohm to Digital: 40 mil). Support conditional rules by layer/region, differential pair gaps, and keepout zones around RF components. DRC checks geometry only; supplement with EM simulation (HFSS, ADS Momentum) to verify actual isolation at frequency.

Related Terms

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