Active Components
Class E Amplifier
In every linear amplifier class, power is wasted because voltage and current coexist in the transistor at the same time. Nathan Sokal eliminated this problem in 1975 by treating the transistor not as a controlled current source but as a switch. When the switch is closed, current flows through near-zero resistance. When open, voltage builds across an open circuit. The load network, a carefully tuned combination of shunt capacitance and series resonance, shapes the drain voltage so that it glides smoothly to zero at exactly the moment the switch closes. No voltage times current overlap means no dissipation. Theoretical efficiency: 100%.
Switching Away the Overlap Problem
Class E Load Network Design Equations
Zero-voltage switching (ZVS) conditions at switch turn-on:
VDS(ton) = 0 and dVDS/dt(ton) = 0
Shunt capacitance (including device Coss):
Cshunt = 0.1836 / (ω × Rload)
Series inductance:
Lseries = 1.1525 × Rload / ω
Optimum load resistance:
Rload = 0.5768 × VDD² / Pout
Example: 10 W at 2 GHz, VDD = 28 V:
Rload = 0.5768 × 784 / 10 = 45.2 Ω
Cshunt = 0.1836 / (2π × 2×109 × 45.2) = 0.32 pF
If the GaN device has Coss = 0.4 pF, it exceeds the design requirement. The device is too large for this frequency and power; select a smaller die or lower VDD.
VDS(ton) = 0 and dVDS/dt(ton) = 0
Shunt capacitance (including device Coss):
Cshunt = 0.1836 / (ω × Rload)
Series inductance:
Lseries = 1.1525 × Rload / ω
Optimum load resistance:
Rload = 0.5768 × VDD² / Pout
Example: 10 W at 2 GHz, VDD = 28 V:
Rload = 0.5768 × 784 / 10 = 45.2 Ω
Cshunt = 0.1836 / (2π × 2×109 × 45.2) = 0.32 pF
If the GaN device has Coss = 0.4 pF, it exceeds the design requirement. The device is too large for this frequency and power; select a smaller die or lower VDD.
Switched-Mode PA Class Comparison
| Class | Peak VDS | Waveform Shape | Theoretical η | Practical η at 2 GHz | Signal Compatibility |
|---|---|---|---|---|---|
| E | 3.56 × VDD | Half-sinusoidal V, rectangular I | 100% | 75 to 85% | Constant envelope only |
| F | 2.0 × VDD | Squared V, half-sine I | 100% | 70 to 80% | Constant envelope only |
| F−1 | 3.14 × VDD | Half-sine V, squared I | 100% | 70 to 80% | Constant envelope only |
| D | 2.0 × VDD | Square wave V | 100% | <1 GHz only | Constant envelope only |
Common Questions
Frequently Asked Questions
Why can Class E beat Class AB efficiency?
Class AB has simultaneous voltage and current in the transistor (V×I = heat). Class E uses the transistor as a switch: current flows through near-zero Ron when on, voltage is high but current is zero when off. The load network ensures zero voltage at turn-on. No overlap = no dissipation.
What limits practical efficiency?
Finite Ron (2 to 5% loss), finite switching speed (V-I overlap during transitions at GHz), and device Coss exceeding the design shunt capacitance. At 2 GHz, practical Class E achieves 75 to 85% drain efficiency.
Can Class E handle OFDM signals?
Not directly (it is a constant-envelope topology). Use envelope tracking (modulate VDD) or outphasing (two Class E PAs with Chireix combining) to reconstruct amplitude modulation while maintaining high efficiency.
See Also