Quantum Computing & Software

Cirq

/sirk/
An open-source Python framework developed by Google for creating, simulating, and running quantum circuits on NISQ processors. Unlike higher-level frameworks, Cirq provides direct control over qubit topology, gate scheduling (moments), and device noise models, enabling hardware-aware circuit optimization. Cirq is the primary interface for Google's superconducting transmon processors (Sycamore, Weber) operating at 4 to 8 GHz and controlled by calibrated microwave pulses at 10 to 20 mK, bridging quantum algorithm design with the physical RF control layer of circuit QED hardware.
Category: Quantum Computing & Software
Language: Python
Hardware: Google Sycamore/Weber

Understanding Cirq

Quantum programming frameworks translate abstract quantum algorithms into sequences of physical operations on real hardware. Cirq is designed from the ground up for NISQ-era processors where qubit count is limited (50 to 100), gate fidelities are imperfect (99 to 99.9%), and circuit depth must be minimized to avoid decoherence. Its core abstraction is the "moment," a time slice containing all gates that execute simultaneously. This explicit scheduling maps directly to the physical timing of microwave control pulses, making it natural for RF engineers to reason about gate ordering, crosstalk windows, and idle qubit decoherence.

Each Cirq gate corresponds to a specific microwave operation. Single-qubit rotations (X, Y, Z gates and arbitrary rotations) are implemented as shaped microwave drive pulses at the qubit's transition frequency (4 to 6 GHz), using DRAG (Derivative Removal by Adiabatic Gate) pulse envelopes to suppress leakage to the third energy level. Pulse durations are 20 to 50 ns with calibrated amplitudes determining the rotation angle. Two-qubit gates (sqrt-iSWAP on Google hardware, CZ on some configurations) use frequency-tuning pulses on flux-bias lines to bring qubits into resonance with a coupling element for 30 to 100 ns. Measurement gates trigger dispersive readout: a microwave probe at 6 to 8 GHz applied to the readout resonator for 500 to 1,000 ns, with the qubit-state-dependent phase shift amplified by a Josephson parametric amplifier. Cirq's noise models simulate all these RF-level imperfections (T1 decay, T2 dephasing, gate crosstalk, readout assignment errors) for realistic circuit performance prediction.

Gate-to-Pulse Mapping

Single-Qubit Gate (X rotation):
θ = Ω · tpulse   [rad, where Ω = Rabi frequency]

Two-Qubit Gate (sqrt-iSWAP):
tgate = π / (4J)   [s, where J = qubit-qubit coupling]

Readout SNR:
SNR = 2χ / κ · √(κ · tmeas · nphoton)

Where Ω = microwave drive amplitude (10 to 100 MHz), J = coupling rate (1 to 10 MHz), χ = dispersive shift (~1 MHz), κ = readout resonator linewidth, tmeas = measurement time (500 to 1,000 ns), nphoton = readout photon number (~5).

Quantum Framework Comparison

FrameworkDeveloperNative HardwareNative Gate SetAbstraction Level
CirqGoogleSycamore/Weber√iSWAP + 1QLow (moments)
QiskitIBMEagle/HeronCX + 1QMedium (DAG)
PennylaneXanaduMulti-backendVariousHigh (ML-focused)
Amazon BraketAWSIonQ, Rigetti, IQMVariousHigh (cloud)
StimGoogleSimulation onlyCliffordLow (stabilizer)
Common Questions

Frequently Asked Questions

How does Cirq differ from Qiskit?

Cirq exposes gate scheduling via "moments" (explicit time slices), mapping directly to physical microwave pulse timing. Qiskit uses a DAG-based representation with implicit parallelism. Cirq targets Google's √iSWAP gate set; Qiskit targets IBM's CX gates. Cirq's direct pulse mapping is particularly useful for RF engineers working on qubit control systems.

What is the connection between Cirq and microwave hardware?

Every Cirq gate maps to a physical microwave operation: single-qubit gates are DRAG pulses at 4 to 6 GHz (20 to 50 ns), two-qubit gates are flux-bias frequency-tuning pulses (30 to 100 ns), and readout is a dispersive probe at 6 to 8 GHz (500 to 1,000 ns). Cirq noise models simulate T1 decay, T2 dephasing, crosstalk, and readout errors at the RF level.

How does Cirq handle noise-aware optimization?

Device-specific noise models capture calibrated per-qubit and per-gate error rates. Cirq routes logical circuits onto physical topology (grid connectivity), selects lowest-error paths, and decomposes arbitrary gates into native √iSWAP + rotations. Built-in optimization passes merge gates, compact moments, and cancel adjacent inverses.

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