Why not just simulate everything in the 3D EM solver?

3D Electromagnetic solvers (like HFSS or CST) are 'passive' solvers. They solve Maxwell's equations for the physical metals and dielectrics, but they cannot simulate 'active' non-linear components like a GaN transistor turning on and off or a mixer generating harmonics. Furthermore, 3D EM simulations take hours to run. If you want to optimize the value of a single tuning capacitor, you cannot wait 4 hours for every iteration. Co-simulation leaves the heavy metal physics to the EM solver and the fast, active math to the circuit solver.

How does Co-Simulation actually work?

The designer takes the physical PCB layout (the copper traces and ground planes) and places 'internal ports' exactly where the transistors and surface-mount capacitors will go. The 3D EM solver runs once, generating a massive multi-port S-parameter file (often with 20+ ports) that perfectly maps how all the traces couple to each other. This block is then imported into the schematic solver. The designer connects the active transistor models and tunable capacitors to the ports of that block. They can now slide a tuning bar to change a capacitor value, and the schematic solver updates instantly, while still retaining the exact physical physics of the board.

What failures does this methodology prevent?

It prevents layout-induced coupling failures. In a pure schematic simulation, an inductor and a capacitor might be wired together, but the software assumes they do not interact through the air. In reality, if those two components are placed close together on the PCB, magnetic fields from the inductor will couple into the capacitor pads, completely changing the circuit's frequency response. Co-simulation captures this physical cross-talk, ensuring the simulation matches the real-world bench measurements.

Simulation & Design

Circuit-EM Co-Simulation

A designer builds an amplifier schematic that shows perfect 20 dB gain at 5 GHz. They layout the PCB, manufacture it, and test it. The bench measurement shows the gain dropping off a cliff at 4.5 GHz. The schematic failed because it assumed the copper traces connecting the components were "ideal wires." In reality, those traces acted as parasitic inductors, and two adjacent traces magnetically coupled to each other, creating a feedback loop. To fix this, the designer uses Circuit-EM Co-Simulation. They take the physical PCB layout and simulate it in a 3D Electromagnetic solver, generating a massive S-parameter file that captures every parasitic physical interaction on the board. They import this block back into the schematic solver and connect their active transistor models to it. Now, when they simulate, the circuit solver instantly calculates the non-linear amplifier physics while routing it entirely through the rigorous 3D physics of the layout. The simulation drops to 4.5 GHz, perfectly matching reality, allowing the designer to fix the layout before ordering another board.

Category: Simulation & Design

Methodology: Multi-port EM Extraction + Schematic Tuning

Goal: Capture physical parasitics with schematic speed

The Co-Simulation Workflow

Phase	Tool Used	Action Performed	Compute Time
1. Layout Design	Layout Editor	Draw copper traces, vias, and ground planes.	Manual
2. Port Definition	Layout Editor	Place internal ports across gaps where components go.	Minutes
3. Extraction	2.5D or 3D EM Solver	Solve Maxwell's equations for the passive layout.	Hours
4. Co-Simulation	Circuit Solver (Schematic)	Attach transistors to the EM block and tune/optimize.	Seconds

Internal Port Mathematics:
When generating the EM block, every component gap becomes an internal port. An amplifier with an input port, output port, and 5 surface-mount capacitors requires a 7-port S-parameter matrix.

[S] = 7x7 Matrix (49 individual S-parameters)
This matrix maps exactly how much energy couples from Port 1 to Port 7 (cross-talk), how much reflects off the pad at Port 3 (parasitic capacitance), and how the ground via inductance affects Port 4. The circuit solver simply multiplies this massive passive matrix by the active transistor models.

Common Questions

Frequently Asked Questions

Why not just use a 3D EM solver for everything?

Because 3D EM solvers (like HFSS or CST) are passive. They do not know how a transistor compresses, how it generates harmonics, or how its bias voltage affects its impedance. Furthermore, if you want an optimizer to try 500 different capacitor values to find the best match, running a 4-hour 3D EM simulation 500 times would take months. Co-simulation allows the fast schematic solver to handle the components, achieving optimization in seconds.

What is an "Internal Port"?

In standard EM simulation, ports are placed at the edges of the board (like SMA connectors). For co-simulation, you must place 'internal ports' directly on the layout wherever a component will sit. These act as mathematical insertion points. The EM solver calculates the physics of the metal up to that point, and the schematic solver injects the component's physics into that exact physical location.

When does schematic-only design fail?

As frequencies rise above 1 GHz, components get physically closer together relative to the wavelength. In a schematic, two inductors placed side-by-side do not interact. On a real PCB, their magnetic fields couple together, creating a transformer. If you do not EM-extract the layout and run a co-simulation, your schematic will completely ignore this coupling and fail on the test bench.

Related Terms

← Circuit Envelope Clapp Oscillator →

System Workflow

Parasitic Coupling Predictor

Upload your multi-port EM extraction S-parameter block. Inject a signal into Port 1 and instantly visualize the magnitude of unwanted magnetic and capacitive cross-talk leaking into all other internal component ports on your layout.

Analyze Layout Coupling