Why are CIC filters used instead of FIR filters for decimation?

An FIR filter operating at the high input sample rate requires all multiplications to run at that rate. For a 1 GSa/s input decimated by 100, a 100-tap FIR at 1 GHz requires 100 billion multiplications per second. A CIC achieves equivalent decimation using only additions at 1 GHz and subtractions at 10 MHz (the output rate), with zero multiplications. The FPGA resource savings are enormous: a 5-stage CIC decimator uses roughly 5 adders and 5 delays, while the equivalent FIR would need hundreds of multipliers. CIC is always the first decimation stage; a small FIR compensation filter follows at the lower rate to correct the CIC's passband droop.

What is passband droop and how is it compensated?

The CIC frequency response is sinc-shaped: |H(f)| = |sin(pi*R*M*f/f_s) / sin(pi*f/f_s)|^N, where R is decimation ratio, M is differential delay, and N is the number of stages. This sinc shape causes the passband to droop (attenuate) at frequencies away from DC. For a 5-stage CIC with R=10, the passband droop at 80% of the output Nyquist is about 4 dB. A small FIR compensation filter (typically 15 to 31 taps) with an inverse-sinc response runs at the decimated output rate to flatten the passband. This CIC + compensation FIR combination is the standard digital receiver decimation architecture.

How do you choose the number of CIC stages?

More stages (N) increase stopband rejection: the alias rejection is approximately N * 20*log10(R) dB where R is the decimation ratio. For R=10 and N=3, rejection is about 60 dB. For R=10 and N=5, rejection is about 100 dB. But more stages increase the bit growth: the output word width grows by N*log2(R*M) bits. For R=10, M=1, N=5: growth = 5*log2(10) ≈ 17 bits. Starting from a 14-bit ADC, the CIC output needs 31 bits. More stages also increase passband droop. Typical designs use N=3 to 5 stages and follow with a compensation FIR.

Signal Processing

CIC Filter

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A Cascaded Integrator-Comb filter is a multiplierless digital filter that achieves efficient sample rate conversion using only additions, subtractions, and delays. CIC filters are the universal first-stage decimator in FPGA-based digital receivers, SDR platforms, and sigma-delta ADC output chains because they consume minimal logic resources while providing high decimation ratios (10x to 1000x) with adequate alias rejection.

Category: Signal Processing

Abbreviation: Cascaded Integrator-Comb

Operations: Add/subtract only (no multiply)

Understanding the CIC Filter

A CIC filter consists of N integrator stages operating at the high sample rate, followed by a rate change (downsampler for decimation, upsampler for interpolation), followed by N comb stages at the low sample rate. Each integrator is a running accumulator: y[n] = y[n−1] + x[n]. Each comb computes the difference: y[n] = x[n] − x[n−RM], where R is the rate change and M is the differential delay (usually 1 or 2).

The cascade of integrators and combs produces a frequency response equivalent to an R×M-tap moving-average filter raised to the N-th power. The response is sinc-shaped with nulls at multiples of f_s,out/M, which naturally suppresses aliased frequency bands during decimation. No multiplications are needed because the coefficients are all unity.

CIC Filter Equations

Transfer function:
H(z) = [(1 − z^−RM) / (1 − z⁻¹)]^N

Frequency response:
|H(f)| = |sin(πRMf/f_s) / sin(πf/f_s)|^N

Alias rejection:
≈ N × 20log₁₀(R) dB (approximate)

Bit growth:
B_out = B_in + N × ⌈log₂(RM)⌉

Example: R=10, M=1, N=4, B_in=14 → B_out = 14 + 4×4 = 30 bits. Alias rejection ≈ 80 dB.

Decimation Filter Chain Architecture

Stage	Filter Type	Rate	Purpose	Resources
1st	CIC (N=3-5)	High (f_s)	Bulk decimation (10-100x)	N adders, N delays
2nd	Half-band FIR	Medium	2x decimation	~15 multipliers
3rd	Compensation FIR	Low (f_out)	Passband droop correction	~31 multipliers
4th (optional)	Channel FIR	Low	Final shaping	~64 multipliers

Common Questions

Frequently Asked Questions

Why CIC instead of FIR for decimation?

A 100-tap FIR at 1 GSa/s needs 100 billion multiplications/second. A 5-stage CIC uses ~5 adders and 5 delays with zero multiplications. The FPGA savings are enormous. CIC does the bulk decimation; a small FIR at the output rate corrects passband droop.

What is passband droop?

CIC has a sinc-shaped response causing 2-6 dB droop at the passband edge. A 15-31 tap inverse-sinc FIR at the decimated rate flattens it. This CIC + compensation FIR is the standard digital receiver architecture.

How many stages should you use?

More stages = better stopband rejection but more bit growth and passband droop. N=3 gives ~60 dB rejection for R=10. N=5 gives ~100 dB. Bit growth is N×log₂(RM) bits. Typical designs use N=3-5.

Related Terms

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