What is the difference between a check node and a variable node in LDPC decoding?

In the Tanner graph, variable nodes represent the coded bits (columns of the parity-check matrix H) and check nodes represent the parity-check equations (rows of H). Variable nodes collect channel LLRs and extrinsic messages from check nodes, then pass updated total LLRs back to the check nodes. Check nodes enforce parity constraints: they compute the reliability that the XOR of all connected bits equals zero and send this information as extrinsic messages to each connected variable node. The iterative exchange between these two node types converges toward the correct codeword.

Digital Communications

Check Node

Q: How does the min-sum algorithm simplify check node processing?

The exact sum-product algorithm computes check-to-variable messages using hyperbolic tangent functions, which require lookup tables or expensive multiplications in hardware. The min-sum algorithm approximates the check node output by taking the minimum absolute LLR among all incoming messages (excluding the target variable node) and multiplying by the product of signs. This replaces tanh/atanh operations with simple comparisons and XORs, reducing hardware complexity by 40 to 60% with only 0.1 to 0.3 dB coding gain loss. Normalized min-sum (scaling the minimum by 0.75 to 0.875) recovers most of the loss.

Q: How many check nodes does a 5G NR LDPC code have?

5G NR defines two LDPC base graphs. Base Graph 1 (BG1) has 46 rows (check nodes per lifting unit) with lifting sizes Z from 2 to 384, supporting up to 46 times 384 = 17,664 check nodes for the largest code block. Base Graph 2 (BG2) has 42 rows for shorter transport blocks. Each check node connects to 3 to 19 variable nodes depending on its row position, with an average check node degree of about 8 for BG1. Modern 5G baseband chips process all check nodes in parallel using layered scheduling, completing one decoding iteration in a single clock cycle per layer.

/chek nohd/

A node in the Tanner graph of a Low-Density Parity-Check (LDPC) code that represents one parity-check equation from the H matrix. During iterative belief-propagation decoding, each check node receives log-likelihood ratio (LLR) messages from its connected variable nodes and computes extrinsic reliability updates using the sum-product or min-sum algorithm, enforcing the constraint that the modulo-2 sum of all connected bits must equal zero. Check node processing is the computational bottleneck in hardware LDPC decoders for 5G NR, Wi-Fi 6/7, and DVB-S2X.

Category: Digital Communications

5G NR BG1: 46 check rows × Z

Degree: 3 to 19 edges

Understanding Check Node

An LDPC code is fully described by its sparse parity-check matrix H, where each row corresponds to one check node and each column to one variable node (coded bit). A "1" at position (i, j) means check node i is connected to variable node j in the Tanner graph, and the parity constraint requires that the XOR of all variable nodes connected to check node i equals zero. The sparsity of H (typically 3 to 20 ones per row) is what makes iterative decoding practical: each check node processes only a small subset of the total codeword bits.

During decoding, messages flow between check nodes and variable nodes in alternating half-iterations. The check-to-variable message from check node c to variable node v conveys the check node's belief about bit v, computed from all other variable nodes connected to c. In the sum-product algorithm (optimal for memoryless channels), this involves products of hyperbolic tangent values. In the min-sum approximation (dominant in hardware), the check node output magnitude is simply the minimum of the incoming LLR magnitudes, and the sign is the product of the incoming signs. This approximation reduces gate count by 40 to 60% with only 0.1 to 0.3 dB performance loss, which normalized or offset min-sum variants can partially recover.

Check Node Message Computation

Sum-Product (exact):
L_c→v = 2 atanh(Π_v'≠v tanh(L_v'→c / 2))

Min-Sum (approximation):
|L_c→v| = min_v'≠v |L_v'→c|
sign(L_c→v) = Π_v'≠v sign(L_v'→c)

Normalized Min-Sum:
|L_c→v| = α × min_v'≠v |L_v'→c| (α = 0.75 to 0.875)

Where L_v'→c = incoming LLR from variable node v' to check node c, and the product/min runs over all variable nodes connected to c except the target v.

LDPC Check Node Parameters by Standard

Standard	Base Graph	Check Rows	Max Degree	Decoding Algorithm
5G NR	BG1	46	19	Layered NMS
5G NR	BG2	42	10	Layered NMS
Wi-Fi 6/7	802.11ax/be	12 to 24	7 to 8	Flooding/Layered MS
DVB-S2X	ETSI	varies	30+	Offset Min-Sum
10G-PON	ITU-T G.9807	varies	6	Min-Sum

Common Questions

Frequently Asked Questions

What is the difference between a check node and a variable node?

Variable nodes represent coded bits (columns of H) and collect channel LLRs plus extrinsic messages from check nodes. Check nodes represent parity-check equations (rows of H) and enforce the constraint that the XOR of all connected bits equals zero. Variable nodes pass updated total LLRs to check nodes, which compute extrinsic reliability and send it back. The iterative exchange converges toward the correct codeword over 5 to 25 iterations.

How does the min-sum algorithm simplify check node processing?

The exact sum-product algorithm uses tanh/atanh functions requiring lookup tables or expensive multiplications. Min-sum approximates the output by taking the minimum absolute LLR among incoming messages and multiplying by the product of signs. This replaces transcendental operations with comparisons and XORs, reducing hardware complexity by 40 to 60% with only 0.1 to 0.3 dB loss. Normalized min-sum (scaling by 0.75 to 0.875) recovers most of the gap.

How many check nodes does a 5G NR LDPC code have?

5G NR Base Graph 1 has 46 check rows with lifting sizes Z from 2 to 384, supporting up to 17,664 check nodes for the largest code block. BG2 has 42 rows for shorter blocks. Each check node connects to 3 to 19 variable nodes depending on row position, with an average degree around 8 for BG1. Modern baseband chips process all check nodes in parallel using layered scheduling, completing one iteration in a single clock cycle per layer.

Related Terms

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