Charged Device Model ESD
Understanding CDM ESD in Semiconductor Devices
In modern semiconductor manufacturing, automated assembly lines, high-speed pick-and-place machines, and robotic handlers are constantly moving chips. During these movements, the sliding of the IC package down a feeder track, or even the contact and separation of the chip from a vacuum nozzle, creates triboelectric charging. The integrated circuit acts as a capacitor, storing this static charge on its leadframes, bond wires, and silicon die. When one of the pins of this charged device touches a grounded metallic guide, socket, or tool, the accumulated charge discharges in a fraction of a nanosecond.
Unlike the Human Body Model (HBM) which simulates a charge transferring from a human finger through a 1.5 kilohm resistor (limiting the discharge speed), a CDM ESD event has no series resistor. The only impedance limiting the current is the internal parasitic resistance and inductance of the chip itself and the contact resistance of the interface. This leads to a discharge path with an impedance of only a few ohms (1 to 10 Ω). As a result, the discharge is incredibly fast, with rise times ranging from 100 to 400 picoseconds, and pulse widths of less than 2 nanoseconds. The peak discharge current can easily exceed 10 amperes, even at a relatively low charging voltage of 500 volts.
For RF and microwave integrated circuits (RFICs), CDM ESD is particularly hazardous. To achieve low noise figures and high operating frequencies (above 10 GHz), RF inputs are designed with very small, low-capacitance transistors and thin gate oxides. Because standard, robust ESD protection diodes (such as large diode clamps) introduce too much parasitic capacitance, which would degrade the RF input match and insertion loss, RF designers must use minimal, high-speed ESD protection schemes. This leaves RF pins highly vulnerable to the high peak current and fast voltage transients of a CDM event. A typical failure mode is the physical dielectric breakdown of the gate oxide or the melting of thin metal interconnects on the silicon die.
Key Equations
Ipeak ≈ Vcharge / Zpath
where Zpath = Rcontact + Rpackage ≈ 1 to 10 Ω (very low impedance).
Electrostatic Charge (Q) and Device Capacitance:
Q = Cdevice × Vcharge
where Cdevice = 1 to 30 pF (varies based on package footprint).
Stored Electrostatic Energy (E):
E = ½ × Cdevice × Vcharge² (low total energy, but high peak power due to transient speed)
Comparison of ESD Stress Models
| Parameter | Charged Device Model (CDM) | Human Body Model (HBM) | Machine Model (MM) - Legacy |
|---|---|---|---|
| Source of Charge | The integrated circuit itself (triboelectric or induction). | Human body (fingertip contact). | Metal tool or machine part. |
| Governing Standard | ANSI/ESDA/JEDEC JS-002 | ANSI/ESDA/JEDEC JS-001 | JEDEC JESD22-A115C (deprecated) |
| Equivalent Circuit | Device capacitance (Cdevice) discharged to ground directly. | 100 pF capacitor in series with a 1500 Ω resistor. | 200 pF capacitor in series with 0 Ω resistor. |
| Pulse Rise Time | 100 to 400 picoseconds (ultra-fast) | 2 to 10 nanoseconds (moderate) | 10 to 30 nanoseconds |
| Peak Current (at 500V) | 5 to 15 Amperes | 0.33 Amperes | 3 to 5 Amperes (tested at 200V) |
| Damage Location | Thin gate oxide dielectric breakdown, metal melting. | Junction burn-out, bulk silicon damage. | Junction burn-out, similar to HBM. |
Frequently Asked Questions
Why is CDM ESD more dangerous for high-frequency RF pins than HBM ESD?
High-frequency RF pins operate at gigahertz speeds, requiring extremely low parasitic capacitance to maintain impedance matching. Standard Human Body Model (HBM) protection circuits utilize large diodes that are slow but handle high energy. While these are effective for slow HBM transients, they are too capacitive for RF lines. Furthermore, a CDM event is much faster than an HBM event, with a rise time under 400 picoseconds. RF pins must be protected by small, low-capacitance, fast-turn-on ESD devices. Because these devices are physically smaller, they can easily be overwhelmed by the massive peak current (up to 15 A) of a CDM discharge, leading to gate oxide rupture.
How does package size affect a device's susceptibility to CDM ESD?
The peak discharge current in a CDM event is directly proportional to the amount of charge the device can store. Since Q = C_device * V_charge, a device with higher physical capacitance will store more charge at a given voltage, resulting in a higher peak current during discharge. Device capacitance is determined by the physical size of the package. A small package like a QFN or bare die has low capacitance (1 to 5 pF) and lower peak currents, while a large BGA package with multiple routing layers and a large substrate ground plane can have a capacitance of 15 to 30 pF, generating peak currents exceeding 15 A that are highly destructive.
What is JEDEC JS-002 and how does it define CDM testing?
JEDEC JS-002 is the joint industry standard that replaces older, separate JEDEC and ESDA CDM test specifications. It defines the Field-Induced Charged Device Model (FI-CDM) test method. During testing, the device under test (DUT) is placed dead-bug style (pins facing up) on a dielectric plate over a field-charging electrode. The electrode is energized to charge the device via capacitance. A grounded probe is then touched to each pin of the DUT, causing a rapid discharge. JS-002 standardizes the target peak currents, rise times, and oscilloscope parameters required to verify that the test setup accurately reproduces real-world manufacturing ESD events.