What simulation engines does Spectre RF include?

Spectre RF is the circuit simulation engine integrated into Virtuoso for RF and mixed-signal analysis: (1) DC analysis: operating point, DC sweep, DC sensitivity. (2) AC analysis: small-signal frequency response, transfer function. (3) Transient: time-domain simulation of nonlinear circuits. (4) PSS (Periodic Steady-State): finds the steady-state response of circuits with periodic excitation (oscillators, mixers, frequency dividers). Much faster than transient for finding steady-state. (5) PSTB (Periodic Stability): Bode plot analysis around the PSS operating point. Used for oscillator phase margin, loop gain in PLLs. (6) PNOISE (Periodic Noise): noise analysis around a periodically time-varying operating point. Computes phase noise of oscillators, noise figure of mixers. This is the key analysis for RF receiver design. (7) PSP (Periodic S-Parameter): large-signal S-parameters. (8) PHAB (Periodic Harmonic Balance): frequency-domain nonlinear analysis. IP3, P1dB, harmonics. Spectre APS and Spectre X are parallelized versions for faster simulation of large circuits.

How does the Virtuoso design flow work?

The Virtuoso custom IC design flow: (1) Schematic capture: design the circuit using foundry PDK transistor models, resistors, capacitors, inductors. Hierarchical design: subcircuits instantiated in top-level. (2) Pre-layout simulation: simulate using Spectre RF to verify performance meets spec (gain, NF, IP3, power, bandwidth). Monte Carlo for yield analysis. Corners: FF, TT, SS, FS, SF across temperature and voltage. (3) Layout: create the physical layout using Virtuoso Layout Suite. Place transistors, draw routing, create guard rings, add decoupling. DRC: design rule checking against foundry rules. LVS: layout vs schematic verification (Assura or PVS). (4) Parasitic extraction: extract R, C, L from the layout using Quantus QRC or StarRC. Create a netlist with parasitics (RCX). (5) Post-layout simulation: re-simulate with extracted parasitics. Verify specs are still met. This is where many designs fail and require layout iteration. (6) EM extraction: EMX or Clarity 3D for inductors, transmission lines, interconnects. (7) Signoff: final DRC/LVS clean, antenna check, ERC. Export GDSII to foundry.

What foundry PDKs work with Virtuoso?

Virtually all major semiconductor foundries provide PDKs (Process Design Kits) for Cadence Virtuoso: TSMC: 180nm to 3nm CMOS, SiGe BiCMOS (55nm, 28nm). The largest foundry. GlobalFoundries: 180nm to 12nm CMOS, SiGe BiCMOS (130nm 8HP, 90nm 9HP), SOI. Samsung: 28nm to 3nm CMOS, including gate-all-around (GAA) at 3nm. Intel Foundry: 16nm to Intel 18A. Tower Semiconductor: 180nm-65nm CMOS, SiGe BiCMOS, RF SOI, BCD. Strong in RF/analog. WIN Semiconductors: GaAs pHEMT, GaN HEMT for MMIC design. PDKs also work with AWR and ADS through integration. IHP: SiGe BiCMOS (130nm SG13G2) for mmWave up to 500 GHz fT. Each PDK includes: transistor models (BSIM, PSP), design rules, pcells (parameterized cells), process corners, Monte Carlo statistical models, and technology files. A PDK is the bridge between circuit design and manufacturing.

RFIC EDA

Cadence Virtuoso

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Industry-standard custom IC platform: Schematic Editor + Layout Suite (DRC/LVS) + Spectre RF (PSS, PNOISE, HB) + EMX/Clarity (EM extraction) + Quantus (parasitic RCX). Supports all major foundry PDKs: TSMC 3nm to 180nm, GF, Samsung, Tower. Used for: RF transceivers, PLLs, LNAs, PAs, ADCs/DACs in CMOS, SiGe, GaAs, GaN.

Sim: Spectre RF

EM: EMX / Clarity

PDK: All foundries

Understanding Cadence Virtuoso

Virtuoso is where silicon meets design. Every major RFIC, from the Wi-Fi transceiver in your phone to the radar front-end in your car, was designed in Virtuoso using foundry PDKs. Its dominance in custom IC design comes from decades of development, universal foundry support, and the Spectre RF simulation engine that handles the unique challenges of RF circuit analysis: periodic steady-state, phase noise, and large-signal S-parameters.

Spectre RF Analysis Types

Cadence Virtuoso:
Industry-standard custom IC platform: Schematic Editor + Layout Suite (DRC/LVS) + Spectre RF (PSS, PNOISE, HB) + EMX/Clarity (EM extraction) + Quantus (parasitic RCX). Supports...

Key specifications:
3 nm | 180 nm | 0 dB | 1 mW

Power: P(dBm) = 10log(P_mW), 0dBm = 1mW

RFIC EDA Comparison

Platform	Circuit Sim	Layout	EM	Strength
Cadence Virtuoso	Spectre RF	Virtuoso	EMX/Clarity	Custom CMOS IC
Keysight ADS	HB/Envelope	Momentum	FEM	GaAs MMIC
Cadence AWR	MWO HB	MWO	AXIEM	PCB RF
Synopsys HSPICE	HSPICE	Custom Compiler	Raphael	Digital/AMS
Ansys HFSS	N/A	N/A	HFSS 3D	Packaging, antenna

Key Equations

Decibel conversion:
Power: dB = 10log(P₂/P₁)
Voltage: dB = 20log(V₂/V₁)

dBm to watts:
P(W) = 10^{(dBm−30)/10}
0 dBm = 1 mW, +30 dBm = 1 W

Wavelength:
λ = c/f = 300/f(MHz) meters

Comparison

Aspect	Cadence Virtuoso Spec	Typical Range	Impact	Design Note
Primary function	Industry-standard custom IC platform: Sc...	Application-dep.	Critical	Verify in sim
Operating range	Supports all major foundry PDKs: TSMC 3n...	Application-dep.	Critical	Verify in sim
Performance	Used for: RF transceivers, PLLs, LNAs, P...	Application-dep.	Critical	Verify in sim
Integration	Understanding Cadence Virtuoso Virtuoso...	Application-dep.	Critical	Verify in sim
Trade-off	Every major RFIC, from the Wi-Fi transce...	Application-dep.	Critical	Verify in sim

Common Questions

Frequently Asked Questions

Spectre RF?

DC, AC, transient + PSS (periodic steady-state), PNOISE (phase noise, mixer NF), PSTB (loop stability), PSP (large-signal S-params). Spectre APS/X for parallel acceleration. The RF analysis engine.

Design flow?

Schematic → pre-layout sim (Spectre, corners, Monte Carlo) → layout (DRC/LVS) → parasitic extraction (Quantus) → post-layout sim → EM extraction (EMX/Clarity) → signoff (GDSII). Iterate until specs met.

Foundry PDKs?

TSMC (3nm-180nm), GF (12nm-180nm, SiGe), Samsung, Tower (RF SOI), WIN (GaAs/GaN), IHP (SiGe 500 GHz fT). PDK = transistor models + design rules + pcells + corners + Monte Carlo.

Related Terms

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