Why is BSIM important for RF IC design?

RFIC simulation accuracy depends entirely on the compact model's ability to predict high-frequency behavior: gain roll-off with frequency (fT and fmax), noise figure (thermal and flicker noise contributions), linearity (third-order intermodulation distortion from nonlinear I-V and C-V characteristics), and substrate coupling (which affects isolation between blocks). BSIM4 and BSIM-CMG include a substrate resistance network, non-quasi-static (NQS) charge model for frequencies approaching fT, induced gate noise correlation with drain noise, and physically-based flicker noise models. Without accurate BSIM parameters, LNA noise figure predictions can be off by 1 to 2 dB, and VCO phase noise predictions can be off by 5 to 10 dB.

What is the difference between BSIM4 and BSIM-CMG?

BSIM4 is the standard model for planar bulk MOSFET devices from 180 nm down to about 20 nm. It uses a surface-potential-based formulation with over 300 parameters covering I-V characteristics, capacitances, noise, self-heating, and junction diodes. BSIM-CMG (Common Multi-Gate) was developed for FinFET and GAA transistors where the gate wraps around a 3D channel (fin or nanosheet). BSIM-CMG captures the electrostatic behavior of multi-gate devices, quantum confinement effects, and the different source-drain symmetry compared to planar devices. For RF at 7 nm and below, BSIM-CMG is essential because the FinFET geometry fundamentally changes the parasitic capacitance structure that dominates high-frequency performance.

How are BSIM model parameters extracted?

Foundries extract BSIM parameters from measured I-V and C-V data on a matrix of test transistors with different widths, lengths, and bias conditions. The extraction flow includes DC I-V fitting (threshold voltage, mobility, output conductance), C-V fitting (oxide capacitance, overlap, fringing, junction), RF S-parameter fitting (substrate network, NQS parameters, gate resistance), and noise fitting (thermal noise coefficient gamma, flicker noise parameters AF and EF). The resulting model card (parameter file) is validated against measured data from silicon and released as part of the foundry's PDK. RF-specific validation includes comparing simulated and measured fT, fmax, NF_min, and IIP3 versus frequency and bias.

RFIC & Semiconductor

BSIM

/bee-sim/ — Berkeley Short-channel IGFET Model

The industry-standard physics-based MOSFET compact model for SPICE simulation, developed at UC Berkeley. BSIM4 models planar MOSFETs (180 nm to 20 nm), while BSIM-CMG (Common Multi-Gate) models FinFET and GAA transistors (14 nm and below). For RFIC design, BSIM includes substrate network models, thermal and induced gate noise, flicker noise, and non-quasi-static charge models critical for accurate LNA, VCO, and mixer simulation.

Category: RFIC & Semiconductor

Versions: BSIM4, BSIM-CMG, BSIM-BULK

Parameters: 300+ (BSIM4)

Understanding BSIM

Every circuit simulation of a CMOS transceiver depends on the compact model that represents each transistor's behavior: DC current vs voltage, capacitance vs bias, noise spectral density vs frequency, and nonlinearity characteristics. BSIM provides physics-based equations for all of these, parameterized by a model card containing 300+ parameters extracted by the foundry from measured silicon data. The model card is part of the Process Design Kit (PDK) that foundries provide to IC designers.

For RF design, the critical BSIM features beyond DC I-V are the substrate resistance network (which models the lossy silicon substrate that limits fmax), the non-quasi-static (NQS) charge model (which captures the finite transit time of carriers across the channel, important above fT/10), induced gate noise and its correlation with drain noise (critical for LNA noise figure optimization), and the flicker (1/f) noise model (which determines VCO phase noise close to the carrier). Inaccurate BSIM parameters lead to first-silicon failures: LNA NF 1 to 2 dB higher than simulated, VCO phase noise 5 to 10 dB worse than predicted.

Key RF Model Parameters

Transit Frequency:
f_T = g_m / (2π (C_gs + C_gd))

Maximum Oscillation Frequency:
f_max = f_T / (2 √(R_g g_ds + R_g C_gd / C_gs × 2π f_T))

Flicker Noise (BSIM4):
S_id(f) = KF × I_ds^AF / (C_ox L^EF f)

Model card parameters: KF (flicker coefficient), AF (current exponent), EF (length exponent).

BSIM Model Family

Model	Device Type	Nodes	RF Features	Status
BSIM3v3	Planar MOSFET	350 nm to 90 nm	Basic substrate, noise	Legacy
BSIM4	Planar MOSFET	180 nm to 20 nm	NQS, substrate network, gate noise	Industry standard
BSIM-CMG	FinFET, GAA	14 nm to 2 nm	Multi-gate parasitics, self-heating	Current
BSIM-BULK	Bulk MOSFET	65 nm to 5 nm	Unified bulk model	Current
BSIM-SOI	FD-SOI	28 nm FD-SOI	Back-gate, thin-body	Current

Common Questions

Frequently Asked Questions

Why is BSIM important for RF?

RFIC accuracy depends on high-frequency models: gain roll-off (fT/fmax), noise figure (thermal + flicker), linearity (IIP3 from nonlinear I-V/C-V), and substrate coupling. Without accurate BSIM parameters, LNA NF can be off by 1 to 2 dB and VCO phase noise by 5 to 10 dB.

BSIM4 vs BSIM-CMG?

BSIM4: planar MOSFETs 180 nm to 20 nm, surface-potential formulation, 300+ parameters. BSIM-CMG: FinFET/GAA for 14 nm and below, captures 3D gate electrostatics, quantum confinement, and changed parasitic capacitance structure that dominates RF performance at advanced nodes.

How are parameters extracted?

Foundries measure I-V, C-V, RF S-parameters, and noise on test transistors of varying W/L. DC fitting (Vth, mobility), C-V fitting (Cox, overlap, fringe), RF fitting (substrate, NQS, Rg), noise fitting (gamma, KF, AF). Validated against fT, fmax, NFmin, IIP3. Released in the PDK model card.

Related Terms

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