Auto-Place
Understanding Auto-Place
Auto-place is the first major step in the physical design flow after schematic capture and netlist generation. The algorithm reads the netlist (every component and every electrical connection between them), then positions every component onto the board outline such that total estimated interconnect length is minimized while obeying physical constraints like component clearances, keep-out zones, and board edges.
The problem is computationally brutal. A modest RF transceiver board with 400 components has more possible placement arrangements than there are atoms in the observable universe. No algorithm can try every possibility, so EDA tools use heuristic optimization, most commonly simulated annealing.
The Simulated Annealing Algorithm
Simulated annealing works by analogy to slowly cooling a molten metal. At high "temperatures," the algorithm freely accepts bad swaps (moves that increase wirelength) to escape local minima. As the temperature cools, the algorithm becomes increasingly selective, only accepting improvements.
P(accept) = e(-ΔC / T)
Where:
ΔC = Change in cost function (positive = worse placement)
T = Current "temperature" (starts high, decreases each iteration)
Cost Function (Half-Perimeter Wirelength):
HPWL = Σ [ (xmax - xmin) + (ymax - ymin) ] for each net
Lower HPWL = better placement.
Why Auto-Place Fails for RF Circuits
The cost function optimizes for wirelength, which is correct for pure digital boards. But for RF circuits, short wirelength is often the wrong objective:
- Coupling: The algorithm places a 2.4 GHz VCO adjacent to a sensitive LNA input because they share power nets, injecting spurious tones into the receive chain.
- Ground plane splits: A component straddling two ground plane zones creates a slot antenna that radiates at the board's resonant frequency.
- Thermal zoning: A power amplifier dissipating 5W needs physical separation from temperature-sensitive crystal oscillators.
- Impedance discontinuities: Arbitrary placement angles force the auto-router to make sharp bends, degrading return loss above 6 GHz.
The Professional RF Layout Workflow
| Step | Method | Why |
|---|---|---|
| 1. RF Signal Chain | Manual | LNA, mixer, filter, IF amp, ADC in a clean linear path with ground stitching between stages. |
| 2. Power Supply | Manual | Switching regulators placed far from sensitive analog blocks to prevent noise injection. |
| 3. Crystal / TCXO | Manual | Reference oscillator close to PLL with short, shielded traces to minimize phase noise pickup. |
| 4. Digital / MCU | Auto-place OK | FPGA decoupling caps, digital bus components, and LED indicators can be auto-placed safely. |
| 5. Decoupling Caps | Constrained auto | 100 nF ceramics constrained to within 2 mm of their IC power pin. |
After manually locking the RF, power, and clock sections, the engineer runs auto-place only on the remaining digital components, then reviews the result before moving to routing.
Frequently Asked Questions
Why does auto-place fail on RF circuits?
Auto-place algorithms optimize for wirelength and congestion, but they have no concept of electromagnetic coupling, ground plane continuity, or controlled-impedance trace routing. An auto-placer will drop a 10 GHz VCO next to a sensitive LNA input because they share nets. An RF engineer must manually isolate those blocks by at least 10 to 15 mm and stitch the ground plane with vias between them.
What algorithm do most auto-place engines use?
Most modern EDA tools use simulated annealing for global placement. The algorithm randomly swaps component positions, evaluates a cost function (typically Half-Perimeter Wirelength), and accepts or rejects the swap based on a Boltzmann probability that decreases as the temperature cools.
Can I use auto-place for mixed-signal boards?
You can use it for digital sections, but never for analog or RF sections. The standard workflow is to manually place the RF signal chain first (LNA, mixer, filter, PA in a clean linear path), lock those components, then let the auto-placer handle the digital controller and decoupling capacitor farm around the locked RF core.