Signal Processing

Aperture Jitter

Q: How does aperture jitter limit ADC performance?

When the sampling clock triggers slightly early or late, the ADC captures a voltage that differs from the intended value. For a sine wave, the maximum slew rate is 2*pi*f_in*A, so the voltage error is proportional to f_in * sigma_t. The resulting SNR ceiling is SNR_jitter = -20*log10(2*pi*f_in*sigma_t). At 1 GHz input with 100 femtosecond jitter, SNR is limited to about 64 dB regardless of ADC bit depth. At 10 GHz, the same jitter limits SNR to 44 dB. This means a 16-bit ADC (96 dB ideal SNR) effectively becomes a 10-bit ADC at 1 GHz if the clock jitter is 100 fs.

Q: What clock jitter is needed for modern RF ADCs?

For a 14-bit ADC (86 dB ideal SNR) to maintain 12 ENOB at 1 GHz input, you need SNR_jitter above 74 dB, which requires sigma_t below 32 femtoseconds. State-of-the-art clock distribution ICs like the TI LMK04832 or ADI HMC7044 achieve 25 to 50 fs rms jitter. The ADC's internal aperture jitter (typically 30 to 100 fs) adds in RSS with the external clock jitter. The total jitter must stay below the target. This is why high-frequency ADC evaluation boards include dedicated low-jitter clock circuits.

Q: Is aperture jitter the same as phase noise?

They are related but not identical. Phase noise is the frequency-domain representation of timing instability: it describes the spectral density of clock edge variations in dBc/Hz at various offsets from the carrier. Aperture jitter is the time-domain rms value of those variations. You can convert between them: sigma_t = sqrt(2 * integral of L(f) df) / (2*pi*f_clk), where L(f) is the single-sideband phase noise. Low close-in phase noise ( 1 MHz) matters for wideband ADC applications.

/ap-er-chur jit-er/

The random, sample-to-sample variation in the exact instant when an ADC's sample-and-hold circuit captures the input voltage. This timing uncertainty creates amplitude errors proportional to the signal's slew rate at the sampling moment, establishing a fundamental SNR ceiling that degrades by 6 dB per octave of input frequency. At GHz input frequencies, even femtosecond-level jitter becomes the dominant limitation on ADC effective resolution.

Category: Signal Processing

Typical values: 25 to 200 fs rms

SNR impact: −6 dB per octave of f_in

Understanding Aperture Jitter

An ideal ADC samples at precisely periodic intervals. In reality, the sampling clock has random timing variations caused by oscillator phase noise, clock buffer noise, and power supply coupling. Each sample is taken at a slightly different time from the ideal, creating an amplitude error equal to the signal's instantaneous slope times the timing error.

For a full-scale sine wave at frequency f_in, the maximum slope is 2πf_inA, where A is the peak amplitude. The rms voltage error from jitter σ_t is σ_v = 2πf_inAσ_t/√2. This error appears as broadband noise, reducing the achievable SNR independent of the ADC's quantization resolution. At high enough frequencies, jitter noise exceeds quantization noise and becomes the bottleneck.

Jitter-Limited SNR

SNR ceiling from aperture jitter:
SNR_jitter = −20 × log₁₀(2π × f_in × σ_t)

Total ADC SNR (combined):
1/SNR_total² = 1/SNR_quant² + 1/SNR_jitter² + 1/SNR_thermal²

Reference values (σ_t = 100 fs):
f_in = 100 MHz → SNR = 84 dB (13.7 ENOB)
f_in = 1 GHz → SNR = 64 dB (10.3 ENOB)
f_in = 5 GHz → SNR = 50 dB (8.0 ENOB)
f_in = 10 GHz → SNR = 44 dB (7.0 ENOB)

A 16-bit ADC (96 dB ideal) becomes effectively 10-bit at 1 GHz with 100 fs jitter.

Jitter Budget by Application

Application	f_in	Target ENOB	Required σ_t	Clock IC Example
Audio (192 kHz)	96 kHz	20	<1 ps	Any crystal oscillator
IF Sampling	200 MHz	12	<100 fs	LMK04832, HMC7044
L-band Direct	1.5 GHz	11	<40 fs	HMC7044, LMX2594+dist
C-band Direct	5 GHz	8	<25 fs	Custom VCXO + distribution

Common Questions

Frequently Asked Questions

How does aperture jitter limit ADC performance?

Jitter causes voltage errors proportional to signal slew rate. SNR_jitter = −20log₁₀(2πf_inσ_t). At 1 GHz with 100 fs, SNR is 64 dB (10.3 ENOB) regardless of bit depth. A 16-bit ADC effectively becomes 10-bit at that frequency.

What clock jitter is needed for modern RF ADCs?

A 14-bit ADC maintaining 12 ENOB at 1 GHz needs σ_t below 32 fs. State-of-the-art clock ICs (TI LMK04832, ADI HMC7044) achieve 25-50 fs. The ADC's internal jitter (30-100 fs) adds in RSS. This is why RF ADC eval boards include dedicated low-jitter clocking.

Is aperture jitter the same as phase noise?

Related but not identical. Phase noise is the frequency-domain spectral density (dBc/Hz). Aperture jitter is the time-domain rms value. Convert via σ_t = √(2∫L(f)df) / (2πf_clk). Close-in phase noise matters for narrowband; wideband phase noise matters for wideband ADC applications.

Related Terms

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